公开(公告)号：US10566520B2

公开(公告)日：2020-02-18

申请号：US16029641

申请日：2018-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L41/00 ,  H01L43/02 ,  G11C11/16 ,  H01L27/02 ,  H01L27/22

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US09857677B2

公开(公告)日：2018-01-02

申请号：US14993103

申请日：2016-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: G03F1/70 ,  G06F17/50 ,  H01L21/033 ,  H01L23/48 ,  H01L23/528

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.

公开(公告)号：US09245822B2

公开(公告)日：2016-01-26

申请号：US14065412

申请日：2013-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: G03F1/36 ,  H01L23/48 ,  G06F17/50 ,  G03F1/70

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.

Abstract translation: 半导体布局图案包括设备布局图案，具有第一尺寸的多个矩形第一虚设图案，具有变化的第二尺寸的多个矩形第二虚设图案以及比第二虚设图形小的多个第一通孔虚设图案， 在第二虚拟图案内的空间范围内。

公开(公告)号：US11877520B2

公开(公告)日：2024-01-16

申请号：US18108003

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L27/02 ,  H10N50/80 ,  G11C11/16 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01L27/0207 ,  H10B61/22

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US20230200256A1

公开(公告)日：2023-06-22

申请号：US18108003

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H10N50/80 ,  G11C11/16 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01L27/0207 ,  H10B61/22

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US20190378971A1

公开(公告)日：2019-12-12

申请号：US16029641

申请日：2018-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L27/02 ,  G11C11/16

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US09269649B2

公开(公告)日：2016-02-23

申请号：US14064219

申请日：2013-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: G06F17/50 ,  H01L23/48 ,  G03F1/70

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.

公开(公告)号：US08788980B2

公开(公告)日：2014-07-22

申请号：US13951095

申请日：2013-07-25

Applicant: United Microelectronics Corp.

Inventor： Jui-Yun Chang ,  Jian-Cheng Chen ,  I-Jen Kao ,  Chih-Wei Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received. A checking process is performed according to the digital database of the layout and the tape-out information and, meanwhile, a mask design procedure for designing a mask pattern corresponding to the layout is performed by using the digital database of the layout, the text information and the tape-out information. A result of the checking process is recorded in an inspection table corresponding to the layout.

Abstract translation: 本发明涉及一种用于在布局上检查模具密封环的方法。 该方法包括以下步骤：接收与至少具有对应于布局的文本信息的设备对应的布局的数字数据库。 接收与布局相对应的磁带输出信息。 根据布局的数字数据库和输出信息进行检查处理，同时，通过使用布局的数字数据库，文本信息来执行用于设计与布局相对应的掩模图案的掩模设计过程 和输出信息。 检查处理的结果记录在与布局对应的检查表中。