公开(公告)号：US20180342618A1

公开(公告)日：2018-11-29

申请号：US15636632

申请日：2017-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Kuo-Chin Hung

IPC: H01L29/78 ,  H01L21/768 ,  H01L23/522 ,  H01L29/45

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa

公开(公告)号：US09887158B1

公开(公告)日：2018-02-06

申请号：US15340982

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC: H01L23/52 ,  H01L29/41 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/41758 ,  H01L29/66628 ,  H01L29/7833

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.

公开(公告)号：US09853123B2

公开(公告)日：2017-12-26

申请号：US14924723

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Kuan-Chun Lin

IPC: H01L29/66 ,  H01L23/535 ,  H01L23/532 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

Abstract: A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.

公开(公告)号：US20170117379A1

公开(公告)日：2017-04-27

申请号：US14924532

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US20160336269A1

公开(公告)日：2016-11-17

申请号：US14709500

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Shu Min Huang ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Pei-Yu Lee ,  Min-Chuan Tsai ,  Chih-Hsun Lin ,  Wu-Sian Sie ,  Jen-Chieh Lin

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor process includes the following steps. A dielectric layer having a recess is formed on a substrate. A barrier layer is formed to cover the recess, thereby the barrier layer having two sidewall parts. A conductive layer is formed on the barrier layer by an atomic layer deposition process, thereby the conductive layer having two sidewall parts. The two sidewall parts of the conductive layer are pulled down. A conductive material fills the recess and has a part contacting the two sidewall parts of the barrier layer protruding from the two sidewall parts of the conductive layer, wherein the equilibrium potential difference between the barrier layer and the conductive layer is different from the equilibrium potential difference between the barrier layer and the conductive material. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成阻挡层以覆盖凹部，由此阻挡层具有两个侧壁部分。 通过原子层沉积工艺在阻挡层上形成导电层，由此导电层具有两个侧壁部分。 导电层的两个侧壁部分被拉下。 导电材料填充凹部，并且具有接触从导电层的两个侧壁部分突出的阻挡层的两个侧壁部分的部分，其中阻挡层和导电层之间的平衡电位差不同于平衡电位差 在阻挡层和导电材料之间。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20210257471A1

公开(公告)日：2021-08-19

申请号：US17246726

申请日：2021-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

公开(公告)号：US20190198628A1

公开(公告)日：2019-06-27

申请号：US15853867

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.

公开(公告)号：US10192826B2

公开(公告)日：2019-01-29

申请号：US15853978

申请日：2017-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC: H01L23/52 ,  H01L29/41 ,  H01L23/528 ,  H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

公开(公告)号：US20170125548A1

公开(公告)日：2017-05-04

申请号：US14924723

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Kuan-Chun Lin

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

Abstract: A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.

公开(公告)号：US09502303B2

公开(公告)日：2016-11-22

申请号：US14682265

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Chun-Tsen Lu ,  Wen-Chin Lin ,  Fu-Shou Tsai

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/285

CPC classification number: H01L21/823475 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823871

Abstract: A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

Abstract translation: 提供一种制造半导体器件的方法。 提供其上形成有绝缘体的基板，其中绝缘体具有多个沟槽，并且相邻的沟槽彼此间隔开。 在绝缘体的上表面和沟槽的侧壁中形成阻挡层，并且阻挡层包括对应于沟槽的悬垂部分。 种子层形成在阻挡层上。 然后，除去形成在阻挡层的上表面上的种子层的上部。 去除阻挡层的上部以暴露绝缘体的上表面。 之后，导体沿种子层沉积以填充沟槽，其中导体的顶表面基本上与绝缘体的上表面对齐。