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    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    11.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20160343855A1

    公开(公告)日：2016-11-24

    申请号：US14737186

    申请日：2015-06-11

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66492 ,  H01L21/2652 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

    Abstract: Provided is a semiconductor device including a substrate, an insulating layer, a conductive layer and at least one spacer. The substrate has at least two shallow trenches therein. The conductive layer is disposed on the substrate between the shallow trenches. The insulating layer is disposed between the substrate and the conductive layer. The at least one spacer is disposed on one sidewall of the conductive layer and fills up each shallow trench. A method of forming a semiconductor device is further provided.

    Abstract translation: 提供了一种半导体器件，其包括衬底，绝缘层，导电层和至少一个间隔物。 衬底中具有至少两个浅沟槽。 导电层设置在浅沟槽之间的衬底上。 绝缘层设置在基板和导电层之间。 至少一个间隔件设置在导电层的一个侧壁上并填充每个浅沟槽。 还提供了形成半导体器件的方法。

    Semiconductor structure
    14.
    发明授权
    Semiconductor structure 有权
    半导体结构

    公开(公告)号：US09472661B1

    公开(公告)日：2016-10-18

    申请号：US14798948

    申请日：2015-07-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Yin Hsiao ,  Chang-Po Hsiung

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

    CPC classification number: H01L29/0653 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/7833

    Abstract: A semiconductor structure suitable for operating under a high voltage condition is provided. According to one aspect of the disclosure, the semiconductor structure includes a substrate, a gate, a source region, a drain region and a field-adjusting structure. The gate is disposed on the substrate. The source region and the drain region are disposed in the substrate and at opposite sides of the gate. The field-adjusting structure is disposed on the substrate at an outer side of one of the source region and the drain region. The field-adjusting structure comprises a first portion and a second portion. The second portion is disposed at an outer side of the first portion. The first portion is connected to the gate. The second portion is connected to the one of the source region and the drain region.

    Abstract translation: 提供适用于在高电压条件下工作的半导体结构。 根据本公开的一个方面，半导体结构包括衬底，栅极，源极区，漏极区和场调整结构。 栅极设置在基板上。 源极区域和漏极区域设置在衬底中并且在栅极的相对侧。 场调整结构在源极区域和漏极区域之一的外侧设置在衬底上。 场调整结构包括第一部分和第二部分。 第二部分设置在第一部分的外侧。 第一部分连接到门。 第二部分连接到源极区域和漏极区域中的一个。

    METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF
    15.
    发明申请
    METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    金属氧化物半导体晶体管器件及其制造方法

    公开(公告)号：US20160233313A1

    公开(公告)日：2016-08-11

    申请号：US15132256

    申请日：2016-04-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

    IPC: H01L29/66 ,  H01L29/40

    CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

    Abstract: A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided. Next, a MOS transistor device is formed on the substrate, the MOS transistor device includes a gate, a source region, a drain region and a spacer. After forming the MOS transistor device, at least a first dummy contact is formed on a drain side of the gate and a gate contact is formed to be electrically connected to the gate. The first dummy contact is spaced apart from a surface of the substrate and electrically connected to the gate contact.

    Abstract translation: 一种用于制造MOS晶体管器件的方法包括以下步骤。 提供了至少包括形成在其中的隔离结构的基板。 接下来，在基板上形成MOS晶体管器件，MOS晶体管器件包括栅极，源极区域，漏极区域和间隔物。 在形成MOS晶体管器件之后，在栅极的漏极侧形成至少第一虚拟触点，并且形成与栅极电连接的栅极接触。 第一虚拟触点与衬底的表面间隔开并且电连接到栅极触点。

    Transistor structure
    16.
    发明授权
    Transistor structure 有权

    公开(公告)号：US11088027B2

    公开(公告)日：2021-08-10

    申请号：US17011270

    申请日：2020-09-03

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

    IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8249

    Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

    High voltage semiconductor device and manufacturing method thereof
    17.
    发明授权
    High voltage semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10903334B2

    公开(公告)日：2021-01-26

    申请号：US16813768

    申请日：2020-03-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Ping-Hung Chiang

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

    Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

    SEMICONDUCTOR DEVICE STRUCTURE
    18.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE 审中-公开

    公开(公告)号：US20180158738A1

    公开(公告)日：2018-06-07

    申请号：US15886717

    申请日：2018-02-01

    Applicant: United Microelectronics Corp.

    Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

    IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L27/092

    Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

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