公开(公告)号：US20250072092A1

公开(公告)日：2025-02-27

申请号：US18948563

申请日：2024-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  Jinyu Liao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417

Abstract: A method of manufacturing a multi-finger transistor structure is provided in the present invention, including forming shallow trench isolations in a substrate to define multiple active areas, forming a gate structure on the substrate, wherein the gate structure includes multiple gate parts and multiple connecting parts, and each gate part traverses over one of the active area, and each connecting part alternatively connect one end and the other end of two adjacent gate parts, so as to form meander gate structure.

公开(公告)号：US12191367B2

公开(公告)日：2025-01-07

申请号：US17752888

申请日：2022-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  Jinyu Liao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417

Abstract: A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

公开(公告)号：US12046659B2

公开(公告)日：2024-07-23

申请号：US17724511

申请日：2022-04-20

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/76898 ,  H01L23/5283 ,  H01L29/0649 ,  H01L29/737

Abstract: A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.

公开(公告)号：US11721772B2

公开(公告)日：2023-08-08

申请号：US17849718

申请日：2022-06-27

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/0688 ,  H01L29/66174

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

公开(公告)号：US11508855B2

公开(公告)日：2022-11-22

申请号：US16739022

申请日：2020-01-09

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

公开(公告)号：US11448318B2

公开(公告)日：2022-09-20

申请号：US16889816

申请日：2020-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hai Biao Yao ,  Su Xing ,  Jinyu Liao ,  Purakh Raj Verma

IPC: H01L23/58 ,  F16J15/06 ,  H05K9/00 ,  H01L23/00

Abstract: The invention provides a seal ring structure, which comprises a substrate, and a seal ring positioned on the substrate, wherein the seal ring comprises an inner seal ring comprising a plurality of inner seal units, wherein each of the inner seal units is arranged at intervals with each other, an outer seal ring comprising a plurality of outer seal units arranged at the periphery of the inner seal ring, wherein each of the outer seal units is arranged at intervals with each other, and a plurality of groups of fence-shaped seal units, wherein at least one group of fence-shaped seal units is positioned between one of the inner seal units and the other adjacent outer seal unit.

公开(公告)号：US20210348684A1

公开(公告)日：2021-11-11

申请号：US16889816

申请日：2020-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAI BIAO YAO ,  Su Xing ,  JINYU LIAO ,  Purakh Raj Verma

IPC: F16J15/06 ,  H05K1/02 ,  H05K1/18 ,  H05K9/00

Abstract: The invention provides a seal ring structure, which comprises a substrate, and a seal ring positioned on the substrate, wherein the seal ring comprises an inner seal ring comprising a plurality of inner seal units, wherein each of the inner seal units is arranged at intervals with each other, an outer seal ring comprising a plurality of outer seal units arranged at the periphery of the inner seal ring, wherein each of the outer seal units is arranged at intervals with each other, and a plurality of groups of fence-shaped seal units, wherein at least one group of fence-shaped seal units is positioned between one of the inner seal units and the other adjacent outer seal unit.

公开(公告)号：US10763170B2

公开(公告)日：2020-09-01

申请号：US15928105

申请日：2018-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Su Xing ,  Ching-Yang Wen

IPC: H01L21/768 ,  H01L27/12 ,  H01L23/48 ,  H01L23/528 ,  H01L29/786 ,  H01L29/417 ,  H01L23/522 ,  H01L21/84

Abstract: A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The semiconductor layer includes a body region disposed between the gate structure and the buried insulation layer. The source doped region and the drain doped region are disposed in the semiconductor layer. A first contact structure penetrates the buried insulation layer and contacts the body region. A second contact structure penetrates the buried insulation layer and is electrically connected with the source doped region. At least a part of the first contact structure overlaps the body region in a thickness direction of the buried insulation layer. The body region is electrically connected with the source doped region via the first contact structure and the second contact structure.

公开(公告)号：US10347733B2

公开(公告)日：2019-07-09

申请号：US15802419

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L29/49 ,  H01L29/06 ,  H01L23/66

Abstract: A radiofrequency switch device includes an insulation layer, a semiconductor layer, a gate structure, a first doped region, a second doped region, an epitaxial layer, a first silicide layer, and a second silicide layer. The semiconductor layer is disposed on the insulation layer. The gate structure is disposed on the semiconductor layer. The first doped region and the second doped region are disposed in the semiconductor layer at two opposite sides of the gate structure respectively. The epitaxial layer is disposed on the first doped region. The first silicide layer is disposed on the epitaxial layer. The second silicide layer is disposed in the second doped region.

公开(公告)号：US20190189738A1

公开(公告)日：2019-06-20

申请号：US16280047

申请日：2019-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun HE ,  Su Xing

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/66 ,  H01L29/24 ,  H01L21/285 ,  H01L21/768 ,  H01L29/45 ,  H01L21/28

CPC classification number: H01L29/0649 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.