公开(公告)号：US20180323302A1

公开(公告)日：2018-11-08

申请号：US16036831

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/823487 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1029 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.

公开(公告)号：US10056490B1

公开(公告)日：2018-08-21

申请号：US15496000

申请日：2017-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/823487 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1029 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which a sidewall of the fin-shaped structure comprises a curve. Specifically, the fin-shaped structure includes a top portion and a bottom portion, a shallow trench isolation (STI) around the bottom portion of the fin-shaped structure, and the curve includes a planar portion extending from the top surface of fin-shaped structure downward and a curved portion extending from the bottom surface of the fin-shaped structure upward.

公开(公告)号：US11587835B2

公开(公告)日：2023-02-21

申请号：US17337446

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.

公开(公告)号：US20200075418A1

公开(公告)日：2020-03-05

申请号：US16676370

申请日：2019-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.

公开(公告)号：US20170170296A1

公开(公告)日：2017-06-15

申请号：US14964546

申请日：2015-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Yu-Ying Lin ,  I-cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Yu-Ren Wang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/02587 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.

公开(公告)号：US09673324B1

公开(公告)日：2017-06-06

申请号：US15246522

申请日：2016-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-I Wu ,  I-Cheng Hu ,  Yu-Shu Lin ,  Shu-Yen Chan ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, including a substrate, a gate structure on the substrate and a source/drain region disposed in the substrate at one side of the gate structure and in at least a part of an epitaxial structure, wherein the epitaxial structure includes a first buffer layer, which is an un-doped buffer layer, including a bottom portion disposed on a bottom surface of the epitaxial structure and a sidewall portion disposed on a concave sidewall of the epitaxial structure, an epitaxial layer which is encompassed by the first buffer layer, and a semiconductor layer which is disposed between the first buffer layer and the epitaxial layer. The source/drain region is disposed in the epitaxial structure.

公开(公告)号：US20170133460A1

公开(公告)日：2017-05-11

申请号：US14936651

申请日：2015-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-I Wu ,  I-cheng Hu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Kun-Hsin Chen ,  Neng-Hui Yang ,  Shu-Yen Chan

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/16 ,  H01L21/283 ,  H01L29/423 ,  H01L21/306 ,  H01L21/225

CPC classification number: H01L21/283 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, including: first, a substrate is provided. Next, at least two gate structures are formed on the substrate, each gate structure including two spacers disposed on two sides of the gate structure. Afterwards, a dry etching process is performed to remove parts of the substrate, so as to form a recess in the substrate, and a wet etching process is performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively. In addition, parts of the spacer are also removed through the wet etching process, and each spacer includes a rounding corner disposed on a bottom surface of the spacer.

公开(公告)号：US20170117410A1

公开(公告)日：2017-04-27

申请号：US14922215

申请日：2015-10-26

Applicant: United Microelectronics Corp.

Inventor： I-cheng Hu ,  Tien-I Wu ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: An epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the Ge concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about ½ to about ¾ of the recess depth.