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公开(公告)号：US10727397B1
公开(公告)日：2020-07-28
申请号：US16261524
申请日：2019-01-29
发明人： Hui-Lin Wang , Yi-Wei Tseng , Meng-Jun Wang , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang , Yu-Ping Wang , Chien-Ting Lin , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , I-Ming Tseng
摘要： A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
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公开(公告)号：US20180068951A1
公开(公告)日：2018-03-08
申请号：US15285471
申请日：2016-10-04
发明人： Ching-Wen Hung , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Chih-Sen Huang
IPC分类号： H01L23/535 , H01L23/528 , H01L27/092 , H01L21/768 , H01L21/8238 , H01L29/66
CPC分类号： H01L23/535 , H01L21/76805 , H01L21/76829 , H01L21/76895 , H01L21/823871 , H01L23/485 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/092 , H01L29/66545
摘要： A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.
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公开(公告)号：US20170103896A1
公开(公告)日：2017-04-13
申请号：US15243986
申请日：2016-08-23
发明人： Ching-Wen Hung , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Chih-Sen Huang , Chun-Hsien Lin
IPC分类号： H01L21/28 , H01L21/285 , H01L29/49 , H01L29/78 , H01L29/06 , H01L29/66 , H01L21/768
CPC分类号： H01L21/28123 , H01L21/28088 , H01L21/28518 , H01L21/76805 , H01L21/76834 , H01L21/76837 , H01L21/76843 , H01L21/76855 , H01L21/76883 , H01L21/76895 , H01L21/76897 , H01L29/0653 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.
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公开(公告)号：US09613969B2
公开(公告)日：2017-04-04
申请号：US14793714
申请日：2015-07-07
发明人： Ching-Wen Hung , Wei-Cyuan Lo , Ming-Jui Chen , Chia-Lin Lu , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Yi-Kuan Wu , Chih-Sen Huang , Yi-Wei Chen , Tan-Ya Yin , Chia-Wei Huang , Shu-Ru Wang , Yung-Feng Cheng
IPC分类号： H01L27/11 , H01L29/76 , H01L21/768 , H01L29/78 , H01L23/535 , H01L21/8234 , H01L21/311
CPC分类号： H01L21/823871 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L23/485 , H01L23/535 , H01L27/0922 , H01L27/1104 , H01L27/1108 , H01L29/7851 , H01L29/7853
摘要： The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
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公开(公告)号：US20160351575A1
公开(公告)日：2016-12-01
申请号：US14793714
申请日：2015-07-07
发明人： Ching-Wen Hung , Wei-Cyuan Lo , Ming-Jui Chen , Chia-Lin Lu , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Yi-Kuan Wu , Chih-Sen Huang , Yi-Wei Chen , Tan-Ya Yin , Chia-Wei Huang , Shu-Ru Wang , Yung-Feng Cheng
IPC分类号： H01L27/11 , H01L21/768 , H01L21/8234 , H01L21/311 , H01L29/78 , H01L23/535
CPC分类号： H01L21/823871 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L23/485 , H01L23/535 , H01L27/0922 , H01L27/1104 , H01L27/1108 , H01L29/7851 , H01L29/7853
摘要： The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
摘要翻译： 本发明提供一种半导体结构，其包括基板，多个翅片结构，多个栅极结构，电介质层和多个接触插塞。 衬底具有存储区域。 翅片结构设置在存储区域中的基板上，每个沿着第一方向延伸。 栅极结构设置在翅片结构上，每个翼结构沿着第二方向延伸。 电介质层设置在栅极结构和鳍结构上。 接触插头设置在电介质层中并电连接到鳍结构中的源极/漏极区域。 从顶部看，接触塞具有梯形或五边形。 本发明还提供了一种形成该方法的方法。
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公开(公告)号：US20240032439A1
公开(公告)日：2024-01-25
申请号：US18373295
申请日：2023-09-27
发明人： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
摘要： A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
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公开(公告)号：US11812669B2
公开(公告)日：2023-11-07
申请号：US17835986
申请日：2022-06-09
发明人： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
摘要： A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号：US11508904B2
公开(公告)日：2022-11-22
申请号：US17308057
申请日：2021-05-05
发明人： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
摘要： A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
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公开(公告)号：US20210035620A1
公开(公告)日：2021-02-04
申请号：US16556170
申请日：2019-08-29
发明人： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
摘要： A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
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公开(公告)号：US20200227473A1
公开(公告)日：2020-07-16
申请号：US16279956
申请日：2019-02-19
发明人： Yi-Hui Lee , I-Ming Tseng , Ying-Cheng Liu , Yi-An Shih , Yu-Ping Wang
摘要： An MRAM structure includes a dielectric layer. A contact hole is disposed in the dielectric layer. A contact plug fills in the contact hole and protrudes out of the dielectric layer. The contact plug includes a lower portion and an upper portion. The lower portion fills in the contact hole. The upper portion is outside of the contact hole. The upper portion has a top side and a bottom side greater than the top side. The top side and the bottom side are parallel. The bottom side is closer to the contact hole than the top side. An MRAM is disposed on the contact hole and contacts the contact plug.
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