公开(公告)号：US09761671B2

公开(公告)日：2017-09-12

申请号：US14585426

申请日：2014-12-30

Applicant: Veeco Instruments, Inc.

Inventor： Ajit Paranjpe ,  Craig Metzner ,  Joe Lamb

IPC: H01L21/18 ,  H01L21/304 ,  H01L21/683 ,  H01L29/20 ,  H01L33/00

CPC classification number: H01L29/2003 ,  H01L21/187 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/6836 ,  H01L33/0075 ,  H01L33/0079 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.

公开(公告)号：US20170125668A1

公开(公告)日：2017-05-04

申请号：US14927604

申请日：2015-10-30

Applicant: Veeco Instruments, Inc.

Inventor： Ajit Paranjpe ,  Boris Druz ,  Katrina Rook ,  Narasimhan Srinivasan

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08

Abstract: This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.

公开(公告)号：US20170076972A1

公开(公告)日：2017-03-16

申请号：US15266308

申请日：2016-09-15

Applicant: Veeco Instruments Inc.

Inventor： Sandeep Krishnan ,  Lukas Urban ,  Alexander Gurary ,  Keng Moy ,  Ajit Paranjpe

IPC: H01L21/687

CPC classification number: H01L21/68771 ,  H01L21/68757 ,  H01L21/68764 ,  H01L21/68785 ,  H01L21/68792

Abstract: A wafer carrier for a plurality of wafers, the wafer carrier having a platen with a plurality of openings and a plurality of wafer retention platforms, the platen configured to rotate about a first axis, the plurality of wafer retention platforms configured to rotate about respective second axes, each of the wafer retention platforms rotatably coupled to one of the plurality of openings by friction reducing bearings, the platen and the plurality of wafer retention platforms and the friction reducing bearings all being constructed of the same material.

Abstract translation: 用于多个晶片的晶片载体，所述晶片载体具有带有多个开口的压板和多个晶片保持平台，所述压板被配置为围绕第一轴线旋转，所述多个晶片保持平台被配置为围绕相应的第二 每个晶片保持平台通过摩擦减小轴承可旋转地联接到多个开口中的一个开口，压板和多个晶片保持平台和减摩轴承全部由相同的材料构成。

公开(公告)号：US20160118291A1

公开(公告)日：2016-04-28

申请号：US14986748

申请日：2016-01-04

Applicant: Veeco Instruments, Inc.

Inventor： Adrian Celaru ,  Todd Arthur Luse ,  Ajit Paranjpe ,  Joseph Scandariato ,  Qingfu Tang

IPC: H01L21/687 ,  C23C16/458

CPC classification number: H01L21/68771 ,  C23C16/4584 ,  H01L21/68764

Abstract: Wafer carriers and methods for moving wafers in a reactor. The wafer carrier may include a platen with a plurality of compartments and a plurality of wafer platforms. The platen is configured to rotate about a first axis. Each of the wafer platforms is associated with one of the compartments and is configured to rotate about a respective second axis relative to the respective compartment. The platen and the wafer platforms rotate with different angular velocities to create planetary motion therebetween. The method may include rotating a platen about a first axis of rotation. The method further includes rotating each of a plurality of wafer platforms carried on the platen and carrying the wafers about a respective second axis of rotation and with a different angular velocity than the platen to create planetary motion therebetween.

Abstract translation: 用于在反应器中移动晶片的晶片载体和方法。 晶片载体可以包括具有多个隔室和多个晶片平台的压板。 压板被构造成围绕第一轴线旋转。 每个晶片平台与隔室中的一个相关联并且被构造成相对于相应的隔室围绕相应的第二轴线旋转。 压板和晶片平台以不同的角速度旋转以在它们之间产生行星运动。 该方法可以包括围绕第一旋转轴旋转压板。 该方法还包括旋转承载在压板上的多个晶片平台中的每一个，并且以相对于第二旋转轴线的速度运送晶片，并以与该压板相对的角速度不同以在其间产生行星运动。

公开(公告)号：US12104242B2

公开(公告)日：2024-10-01

申请号：US16870110

申请日：2020-05-08

Applicant: Veeco Instruments Inc.

Inventor： Alexander I. Gurary ,  Mandar Deshpande ,  Ajit Paranjpe

IPC: C23C16/44 ,  C23C16/02 ,  C23C16/46 ,  C23C16/54 ,  H01J37/32 ,  H05B1/02

CPC classification number: C23C16/0227 ,  C23C16/4412 ,  C23C16/463 ,  C23C16/54 ,  H01J37/32899 ,  H05B1/0233

Abstract: A chemical vapor deposition system for semiconductor wafer production is disclosed. The system includes a process cluster coupled to a first end of a transfer chamber. The process cluster is maintained at a pressure that is lower than atmospheric pressure. The process cluster is also configured to apply epitaxial layers on one or more wafers loaded onto a wafer carrier. The system also includes an automatic factory interface coupled to a second end of the transfer chamber. The automatic factory interface is maintained at atmospheric pressure. The system includes one or more wafer carrier cleaning modules coupled to the automatic factory interface and configured to clean one or more of the wafer carriers without removing the wafer carriers from the chemical vapor deposition system.

公开(公告)号：US20240175132A1

公开(公告)日：2024-05-30

申请号：US18519476

申请日：2023-11-27

Applicant: VEECO INSTRUMENTS INC.

Inventor： Ajit Paranjpe ,  Alexander Gurary ,  Bojan Mitrovic

IPC: C23C16/458 ,  C23C16/448 ,  C23C16/455

CPC classification number: C23C16/4584 ,  C23C16/4481 ,  C23C16/455

Abstract: A multi-wafer metal organic chemical vapor deposition system in which adjacent wafers positioned within the system rotate about their own axes, including a reaction chamber comprising an exhaust system including a peripheral port, a multi-wafer carrier comprising a wafer carrier body and a plurality of wafer carrier discs supported within the wafer carrier body, wherein adjacent wafer carrier discs of the plurality wafer carrier discs are configured and the wafer carrier body are configured to rotate at different speeds, a multi-zone injection block positioned over the wafer carrier body, a central gas port positioned in the center of the wafer carrier body functions as a gas exhaust, and a multi-zone heater assembly positioned beneath the multi-wafer carrier.

公开(公告)号：US20180230596A1

公开(公告)日：2018-08-16

申请号：US15947352

申请日：2018-04-06

Applicant: Veeco Instruments Inc.

Inventor： Bojan Mitrovic ,  Guanghua Wei ,  Eric A. Armour ,  Ajit Paranjpe

IPC: C23C16/458 ,  C23C16/455 ,  H01L21/687 ,  H01L21/02 ,  C30B29/06 ,  C30B25/16 ,  C23C16/46

CPC classification number: C23C16/4585 ,  C23C16/45504 ,  C23C16/45508 ,  C23C16/45591 ,  C23C16/4584 ,  C23C16/46 ,  C30B25/165 ,  C30B29/06 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/68735 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/68785

Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.

公开(公告)号：US20150187888A1

公开(公告)日：2015-07-02

申请号：US14585426

申请日：2014-12-30

Applicant: VEECO INSTRUMENTS, INC.

Inventor： Ajit Paranjpe ,  Craig Metzner ,  Joe Lamb

IPC: H01L29/20 ,  H01L21/683 ,  H01L33/12 ,  H01L33/00 ,  H01L33/32 ,  H01L21/02 ,  H01L21/18

CPC classification number: H01L29/2003 ,  H01L21/187 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/6836 ,  H01L33/0075 ,  H01L33/0079 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.

Abstract translation: 可以采用剥落工艺来在诸如体GaN衬底的高质量结晶氮化物衬底内的预定深度处产生断裂。 第一结晶导电膜层可以沿着断裂线从结晶氮化物衬底分离，并随后结合到包括传统低成本衬底的层叠堆叠。 如果第一结晶导电膜层的剥离表面在所得到的结构中暴露，则该结构可以用作可以生长高质量GaN基器件的衬底。