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公开(公告)号：US10289559B2
公开(公告)日：2019-05-14
申请号：US15166272
申请日：2016-05-27
Applicant: VIA Technologies, Inc.
Inventor： Sheng-Huei Huang , Yi-Lin Lai
IPC: G06F3/06 , G06F11/10 , G06F11/14 , G06F12/02 , G06F12/1009
Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned with a group age parameter. The adjusting of the group age parameters is triggered by a writing instruction of a host. When an age parameter of the group age parameters exceeds a predetermined range, the controller performs a scanning operation to the non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the age parameter, so as to check an error-bit quantity. The controller decides whether the storage block data-moving operation is performed to the non-volatile storage block corresponding to the corresponding logical block address group based on the results of the scanning operation.
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公开(公告)号：US20180329776A1
公开(公告)日：2018-11-15
申请号：US15662254
申请日：2017-07-27
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen , Ying-Che Chung
CPC classification number: G06F11/1068 , G06F11/1004 , G06F11/1048 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/152 , H03M13/2906
Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.
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公开(公告)号：US09318213B2
公开(公告)日：2016-04-19
申请号：US14317138
申请日：2014-06-27
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Chin-Yin Tsai , Yi-Lin Lai
CPC classification number: G11C16/32 , G11C29/023 , G11C29/028 , G11C29/12015
Abstract: An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands.
Abstract translation: 使用闪存的数据存储设备的超频处理。 用于闪速存储器的控制器使用具有各种频率的测试时钟来测试闪存，以确定适合于闪存的至少一个时钟信号。 从测试时钟中选择适合闪存的时钟候选。 闪速存储器以可变频率的方式操作，通过该方式闪存在时钟候选之间切换，使得电磁干扰分布在不同的频带上。
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公开(公告)号：US09305662B2
公开(公告)日：2016-04-05
申请号：US14317108
申请日：2014-06-27
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Chin-Yin Tsai , Yi-Lin Lai
IPC: G11C29/00 , G11C29/08 , G06F12/02 , G11C16/34 , G11C29/12 , G06F12/14 , G11C16/00 , G11C29/04 , G11C29/44
CPC classification number: G11C29/08 , G06F12/0246 , G06F12/1416 , G06F2212/7211 , G11C16/00 , G11C16/349 , G11C29/12015 , G11C2029/0409 , G11C2029/4402
Abstract: An identification technique for physically damaged blocks of a flash memory of a data storage device. In the data storage device, a controller coupled to the flash memory writes data into the flash memory with at least one time stamp corresponding to the data. The time stamp is taken into consideration by the controller to identify the physically damaged blocks of the flash memory, and thereby it is prevented from erroneously identifying a physically undamaged block as bad. Thus, the flash memory is prevented from being erroneously regarded as a write protected memory. The lifespan of the flash memory is effectively prolonged.
Abstract translation: 一种用于数据存储设备的闪存的物理损坏块的识别技术。 在数据存储设备中，耦合到闪速存储器的控制器以对应于数据的至少一个时间戳将数据写入闪速存储器。 由控制器考虑时间标记以识别闪存的物理损坏块，从而防止错误地识别物理上没有损坏的块是不好的。 因此，防止闪存被错误地视为写保护存储器。 闪存的寿命有效延长。
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15.发明授权公开(公告)号：US09111049B2
公开(公告)日：2015-08-18
申请号：US13706579
申请日：2012-12-06
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Yi-Lin Lai , Hao-Hsuan Chiu , Terrance Shih
CPC classification number: G06F13/4022 , G06F1/266 , G06F13/4068 , G06F13/426 , H02J7/0004 , H02J7/007
Abstract: An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result.
Abstract translation: 提供了用于耦合通用串行总线（USB）设备和USB主机的设备。 该装置包括存储器和控制器。 存储器包括一个或多个描述符条目。 控制器被配置为在USB总线上检测到USB设备时获得USB设备的描述符，并将描述符与特定描述符条目进行比较以生成比较结果。 然后控制器根据比较结果启用或禁用USB主机和USB设备之间的链接路径。
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Patent Agency Ranking
公开(公告)号：US11334429B2
公开(公告)日：2022-05-17
申请号：US16985241
申请日：2020-08-05
Applicant: VIA Technologies, Inc.
Inventor： Yi-Lin Lai , Chen-Te Chen , Ying-Che Chung
Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.
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公开(公告)号：US20210303193A1
公开(公告)日：2021-09-30
申请号：US17195551
申请日：2021-03-08
Applicant: VIA Technologies, Inc.
Inventor： Chin-Yin Tsai , Yi-Lin Lai
Abstract: A data storage system and a global deduplication method thereof are provided. The data storage system includes multiple storage devices and one dispatch device. The dispatch device divides an original data corresponding to a data writing request into at least one data chunk. The dispatch device performs a summary calculation on one data chunk, so as to generate a representative value. The dispatch device performs a first distribution calculation on the representative value, so as to determine a destination location corresponding to the representative value. The dispatch device transmits the data chunk and the representative value to at least one destination storage device among the storage devices through a communication network according to the destination location. The at least one destination storage device checks the representative value, so as to determine whether to store the data chunk in a storage space of the at least one destination storage device.
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18.发明授权公开(公告)号：US10318463B2
公开(公告)日：2019-06-11
申请号：US14452784
申请日：2014-08-06
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Chia-Ying Kuo , Yi-Lin Lai
Abstract: An interface controller coupling the main body of an external electronic device to a host, and the electronic device using the interface controller and a control method for the external electronic controller are disclosed. The interface controller has a control unit and a non-volatile memory. The control unit is configured to transmit a termination-on signal to the host when link information retrieved from the main body has been written into the non-volatile memory. When the host issues a link information request in response to the termination-on signal, the control unit uses the link information stored in the non-volatile memory to respond to the link information request.
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公开(公告)号：US20190073262A1
公开(公告)日：2019-03-07
申请号：US15808808
申请日：2017-11-09
Applicant: VIA Technologies, Inc.
Inventor： Ching-Yu Chen , Yi-Lin Lai , Chen-Te Chen
CPC classification number: G06F11/1068 , G06F11/1012 , G11C29/52 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3715 , H03M13/373
Abstract: An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.
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公开(公告)号：US10120597B2
公开(公告)日：2018-11-06
申请号：US15333004
申请日：2016-10-24
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Yao-Shun Hung , Chin-Yin Tsai , Yi-Lin Lai
Abstract: A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein the controller further determines whether the memory chip enters a boot mode for the first time, and when the memory chip enters the boot mode for the first time, the controller accesses the memory to obtain a correct boot image from the boot images and transmits the correct boot image to the host. Further, each boot image includes a plurality of data blocks, and the controller loads a plurality of correct data blocks from one or more of the boot images to obtain the correct boot image.
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