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    In-Memory Deep Neural Network Device Using Spin Orbit Torque (SOT) With Multi-State Weight
    11.
    发明申请
    In-Memory Deep Neural Network Device Using Spin Orbit Torque (SOT) With Multi-State Weight 有权

    公开(公告)号：US20250077834A1

    公开(公告)日：2025-03-06

    申请号：US18954415

    申请日：2024-11-20

    Applicant: Western Digital Technologies, Inc.

    Inventor： Quang LE ,  Xiaoyong LIU ,  Lei XU ,  Brian R. YORK ,  Cherngye HWANG ,  Hisashi TAKANO

    IPC: G06N3/04

    Abstract: The present disclosure is generally related to a deep neural network (DNN) device comprising a plurality of spin-orbit torque (SOT) cells. The DNN device comprises an array comprising n rows and m columns of nodes, each row of nodes coupled to one of n first conductive lines, each column of nodes coupled to one of m second conductive lines, each node of the n rows and m columns of nodes comprising a plurality of SOT cells, each SOT cell comprising: at least one SOT layer, at least one ferromagnetic (FM) layer, and a controller configured to store at least one corresponding weight of an n×m array of weights of a neural network in each of the SOT cell. The FM layer may comprise two or more domains, two or more elliptical arms, or two or more states.

    Spin Orbital Squared (SO-SO) Logic
    13.
    发明申请
    Spin Orbital Squared (SO-SO) Logic 有权

    公开(公告)号：US20240423098A1

    公开(公告)日：2024-12-19

    申请号：US18645189

    申请日：2024-04-24

    Applicant: Western Digital Technologies, Inc. ,  Tokyo Institute of Technology

    Inventor： Quang LE ,  Xiaoyong LIU ,  Brian R. YORK ,  Cherngye HWANG ,  Hisashi TAKANO ,  Nam Hai PHAM

    IPC: H10N50/85 ,  H03K19/18 ,  H10N52/80

    Abstract: The present disclosure generally relate to an integrated circuit utilizing spin orbital-spin orbital (SO-SO) logic. The integrated circuit comprises a plurality of SO-SO logic cells, where each SO-SO logic cell comprises a first spin orbit torque (SOT1) layer, a second spin orbit torque (SOT2) layer, and a ferromagnetic layer disposed between the SOT1 and SOT2 layer. Each SO-SO logic cell is configured for: a first current path that is in plane to a plane of the SOT1 layer, and a second current path that is perpendicular to a plane of the SOT2 layer, the second current path being configured to extend into the ferromagnetic layer. The integrated circuit further comprises a common voltage source connected to each SOT device, and one or more interconnects disposed between adjacent SOT devices of the plurality of SOT devices, the one or more interconnects connecting the adjacent SOT devices together.

    Read Sensor With Ordered Heusler Alloy Free Layer and Semiconductor Barrier Layer
    14.
    发明公开
    Read Sensor With Ordered Heusler Alloy Free Layer and Semiconductor Barrier Layer 审中-公开

    公开(公告)号：US20240194221A1

    公开(公告)日：2024-06-13

    申请号：US18227537

    申请日：2023-07-28

    Applicant: Western Digital Technologies, Inc.

    Inventor： Yuankai ZHENG ,  Susumu OKAMURA ,  Brian R. YORK ,  Zhitao DIAO ,  James Mac FREITAG

    IPC: G11B5/31 ,  G11B5/39

    CPC classification number: G11B5/3146 ,  G11B5/314 ,  G11B5/3929

    Abstract: Embodiments of the present disclosure generally relate to a read sensor utilized in a read head. The read sensor comprises an amorphous break layer disposed on a shield, a seed layer disposed on the amorphous break layer, a first ferromagnetic layer disposed on the seed layer, a barrier layer disposed on the first ferromagnetic layer, and a second ferromagnetic layer disposed on the barrier layer. The amorphous break layer comprises CoFeBTa, the seed layer comprises RuAl, and the barrier layer comprises a semiconductor material, such as ZnSe, ZnTe, ZnO, CuSe, or CuInGaSe. The semiconductor barrier layer reduces the resistance-area product of the read sensor. The amorphous break layer breaks the texture between the shield, which has a FCC texture, and the seed layer, which has a BCC texture. The BCC texture of the seed layer is then inherited by the remaining layers disposed over the seed layer.

    Bismuth Antimony Alloys for Use as Topological Insulators
    18.
    发明申请
    Bismuth Antimony Alloys for Use as Topological Insulators 有权

    公开(公告)号：US20210408370A1

    公开(公告)日：2021-12-30

    申请号：US16917334

    申请日：2020-06-30

    Applicant: Western Digital Technologies, Inc.

    Inventor： Brian R. YORK ,  Cherngye HWANG ,  Alan SPOOL ,  Michael GRIBELYUK ,  Quang LE

    IPC: H01L43/10 ,  H01L27/22 ,  H01L43/06 ,  H01L43/04 ,  H03B15/00

    Abstract: A SOT device includes a bismuth antimony dopant element (BiSbE) alloy layer over a substrate. The BiSbE alloy layer is used as a topological insulator. The BiSbE alloy layer includes bismuth, antimony, AND a dopant element. The dopant element is a non-metallic dopant element, a metallic dopant element, and combinations thereof. Examples of metallic dopant elements include Ni, Co, Fe, CoFe, NiFe, NiCo, NiCu, CoCu, NiAg, CuAg, Cu, Al, Zn, Ag, Ga, In, or combinations thereof. Examples of non-metallic dopant elements include Si, P, Ge, or combinations thereof. The BiSbE alloy layer can include a plurality of BiSb lamellae layers and one or more dopant element lamellae layers. The BiSbE alloy layer has a (012) orientation.

    Deep Neural Network Device Based on Dual Spin Orbit Torque (SOT) Devices
    19.
    发明申请
    Deep Neural Network Device Based on Dual Spin Orbit Torque (SOT) Devices 有权

    公开(公告)号：US20250148274A1

    公开(公告)日：2025-05-08

    申请号：US18645195

    申请日：2024-04-24

    Applicant: Western Digital Technologies, Inc. ,  Tokyo Institute of Technology

    Inventor： Quang LE ,  Xiaoyong LIU ,  Brian R. YORK ,  Hisashi TAKANO ,  Nam Hai PHAM

    IPC: G06N3/063 ,  H10N50/20

    Abstract: The present disclosure generally relates to a deep neural network (DNN) device utilizing spin orbital-spin orbital (SO-SO) devices. The SO-SO devices each includes two SOT layers, a first spin orbit torque (SOT1) layer, a second spin orbit torque (SOT2) layer, and a ferromagnetic layer disposed between the SOT1 and SOT2 layer. Each SO-SO device further comprises three terminals, one per each SOT layer, for in plane current flow to or from the respective SOT layer, and one for perpendicular current flow through multiple layers, or the overall stack, of the SO-SO device. The SO-SO device thus efficiently provides spin-to-charge and charge-to-spin mechanisms in the same device, and can be flexibility configured to perform various functions of a neural node of a DNN. These functions include storing programmed weights, multiplying inputs and weights and summing such multiplication results, and performing an activation function to determine a neural node output.

    Spin-Orbit Torque SOT Reader with Recessed Spin Hall Effect Layer
    20.
    发明申请
    Spin-Orbit Torque SOT Reader with Recessed Spin Hall Effect Layer 有权

    公开(公告)号：US20250095673A1

    公开(公告)日：2025-03-20

    申请号：US18368220

    申请日：2023-09-14

    Applicant: Western Digital Technologies, Inc.

    Inventor： Quang LE ,  Xiaoyong LIU ,  Fan TUO ,  Brian R. YORK ,  Cherngye HWANG ,  Hisashi TAKANO

    IPC: G11B5/127

    Abstract: The present disclosure generally relates to a magnetic recording head comprising one or more spin-orbit torque (SOT) devices, the SOT devices each comprising a bismuth antimony (BiSb) layer. The magnetic recording head comprises a SOT device comprising a first shield extending to a media facing surface (MFS), a seed layer disposed over the first shield, the seed layer being disposed at the MFS, a free layer disposed on the seed layer, the free layer being disposed at the MFS, a bismuth antimony (BiSb) layer disposed over the free layer, the BiSb layer being recessed from the MFS, a second shield disposed over the BiSb layer, the second shield extending to the MFS, and a shield notch coupled to the second shield, the shield notch being disposed between the first shield and the second shield. The magnetic recording head may be a two-dimensional magnetic recording head comprising two SOT devices.

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