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公开(公告)号：US20180247944A1
公开(公告)日：2018-08-30
申请号：US15892350
申请日：2018-02-08
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Riichiro Shirota
IPC: H01L27/1157 , H01L27/11582 , H01L27/11573
Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.
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公开(公告)号：US20160163391A1
公开(公告)日：2016-06-09
申请号：US14826204
申请日：2015-08-14
Applicant: Winbond Electronics Corp.
Inventor： Riichiro Shirota
CPC classification number: G11C16/10 , G11C7/12 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/32 , G11C16/3459
Abstract: A programming method of an NAND flash memory is provided, for narrowing a distribution width of a threshold voltage. The method includes a step of verification reading for verifying a threshold voltage of a selected memory cell after a programming voltage is applied to a selected word line. The verification reading further includes a step of pre-charging a voltage to a bit line, a step of discharging the pre-charged bit line to a source line, and a step of reading the voltage of the bit line after the discharging step. Regarding the discharge period from starting the discharging of the bit line to starting the read out, the discharge period of the verification reading after the initial programming voltage is applied is set longer than the discharge period of the verification reading after the subsequent programming voltage is applied.
Abstract translation: 提供了NAND闪存的编程方法，用于缩小阈值电压的分布宽度。 该方法包括在将编程电压施加到所选择的字线之后验证读取以验证所选存储单元的阈值电压的步骤。 验证读取还包括对位线进行电压预充电的步骤，将预充电位线放电到源极线的步骤以及在放电步骤之后读取位线的电压的步骤。 关于从开始放电的位线到开始读出的放电期间，施加了初始编程电压之后的验证读取的放电周期被设定为比后续编程电压施加之后的验证读取的放电周期长 。
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公开(公告)号：US20150003163A1
公开(公告)日：2015-01-01
申请号：US14272516
申请日：2014-05-08
Applicant: Winbond Electronics Corp.
Inventor： Riichiro Shirota
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3427
Abstract: A programming method for suppressing deterioration of an insulating layer in a memory cell is provided. In the programming method for a flash memory of the invention, a cell unit including programming units that have been programmed is electrically isolated from a bit line; a cell unit not including programming units is electrically coupled with the bit line; a programming voltage is applied to selected word lines; and a pass voltage is applied to non-selected word lines. Moreover, during a period of applying the programming voltage, carriers are generated in a P-well, and hot carriers passing through a depletion region and accelerated by an electric field are injected into the memory cell.
Abstract translation: 提供一种用于抑制存储单元中的绝缘层的劣化的编程方法。 在本发明的闪速存储器的编程方法中，包括已被编程的编程单元的单元单元与位线电隔离; 不包括编程单元的单元单元与位线电耦合; 对所选择的字线施加编程电压; 并且将通过电压施加到未选择的字线。 此外，在施加编程电压的期间，在P阱中产生载流子，通过耗尽区域并通过电场加速的热载流子被注入到存储单元中。
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公开(公告)号：US12250816B2
公开(公告)日：2025-03-11
申请号：US17489826
申请日：2021-09-30
Applicant: Winbond Electronics Corp.
Inventor： Riichiro Shirota
Abstract: A NAND flash memory and manufacturing method thereof are provided. The NAND flash memory is capable of preventing a short circuit between gates extending along a vertical direction. The NAND flash memory includes a substrate; a plurality of channel stacks formed on the substrate and extending along an X direction; an interlayer dielectric formed between the channel stacks; a plurality of trenches formed apart from each other in the interlayer dielectric and arranged along a Y direction; an insulator stack including a charge storage layer formed to cover sidewalls of each of the trenches; and a plurality of conductive vertical gates elongating along the vertical direction in a space formed by the insulator stack in each of the trenches and extending along the Y direction.
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公开(公告)号：US11778819B2
公开(公告)日：2023-10-03
申请号：US16935199
申请日：2020-07-22
Applicant: Winbond Electronics Corp.
Inventor： Riichiro Shirota
CPC classification number: H10B43/27 , G11C7/18 , H01L29/66833 , H01L29/7926 , H10B43/10 , H10B43/35
Abstract: A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.
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Patent Agency Ranking
公开(公告)号：US20220328513A1
公开(公告)日：2022-10-13
申请号：US17227383
申请日：2021-04-12
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Riichiro Shirota
IPC: H01L27/11582 , H01L27/11556 , H01L27/1157 , H01L27/11524
Abstract: A memory device and method of fabricating the same are provided. The memory device includes a substrate, a stacked structure, a channel layer, and a charge storage structure. The stacked structure is located on the substrate and includes a plurality of insulating layers and a plurality of conductive layers stacked alternately, and the stacked structure has holes. The channel layer is located in the hole and includes a first part and a second part. The number of grain boundaries in the second part is less than the number of grain boundaries in the first part. The charge storage structure is located between the first part and the plurality of conductive layers, and the charge storage structure and the second part sandwich the first part therebetween.
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公开(公告)号：US20220115400A1
公开(公告)日：2022-04-14
申请号：US17489826
申请日：2021-09-30
Applicant: Winbond Electronics Corp.
Inventor： Riichiro Shirota
IPC: H01L27/11582 , H01L27/11565
Abstract: A NAND flash memory and manufacturing method thereof are provided. The NAND flash memory is capable of preventing a short circuit between gates extending along a vertical direction. The NAND flash memory includes a substrate; a plurality of channel stacks formed on the substrate and extending along an X direction; an interlayer dielectric formed between the channel stacks; a plurality of trenches formed apart from each other in the interlayer dielectric and arranged along a Y direction; an insulator stack including a charge storage layer formed to cover sidewalls of each of the trenches; and a plurality of conductive vertical gates elongating along the vertical direction in a space formed by the insulator stack in each of the trenches and extending along the Y direction.
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公开(公告)号：US11271005B2
公开(公告)日：2022-03-08
申请号：US16893411
申请日：2020-06-04
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Riichiro Shirota
IPC: H01L27/1157 , H01L27/11573 , H01L29/792 , H01L27/11582 , H01L21/28
Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.
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公开(公告)号：US10916558B2
公开(公告)日：2021-02-09
申请号：US16235329
申请日：2018-12-28
Applicant: Winbond Electronics Corp.
Inventor： Riichiro Shirota
IPC: H01L27/11582 , H01L27/11565 , H01L27/1157 , G11C16/16 , G11C16/26 , H01L21/28 , H01L27/11556 , H01L27/11519 , H01L27/11524
Abstract: NOR flash memory that includes three-dimensional memory cells is provided. In the NOR flash memory of the present disclosure, one memory cell includes one memory transistor and one selection transistor. A common source 5 is formed over a silicon substrate 9, and an active region 3 extending in a vertical direction to electrically connect to the common source 5 is formed. A control gate 4 of the memory transistor and a selection gate line 2 of the selection transistor are formed to surround a side portion of the active region 3, and a top portion of the active region 3 is electrically connected to a bit line 1.
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公开(公告)号：US20170092368A1
公开(公告)日：2017-03-30
申请号：US15277992
申请日：2016-09-27
Applicant: Winbond Electronics Corp.
Inventor： Katsutoshi Suito , Riichiro Shirota
IPC: G11C16/14 , G11C16/04 , H01L27/115 , G11C16/34
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C16/3472 , G11C16/3477 , H01L27/11524
Abstract: An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).
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