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公开(公告)号：US10581450B1
公开(公告)日：2020-03-03
申请号：US16249230
申请日：2019-01-16
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , Bob W. Verbruggen , Christophe Erdmann , Roberto Pelliconi
Abstract: Apparatus and associated methods relating to a digital-to-analog converter (DAC) include a programmable resistance network coupled between a voltage supply node VDD and a switch cell circuit to provide a predetermined resistance in response to the VDD and current IS of the switch cell circuit. In an illustrative example, the DAC may include a switch cell circuit comprising one or more switch cells connected in parallel. Each switch cell may include a differential gain circuit having a first branch coupled to a second branch at an input of a current source. The programmable resistance may include a variable resistance configured to adjust a voltage (Vbias) supplied to the switch cell circuit in response to a control signal. By introducing the programmable resistance network, predetermined bias and/or gain values may be dynamically adjusted with a constant board-level power supply VDD.
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公开(公告)号：US10218372B1
公开(公告)日：2019-02-26
申请号：US15939257
申请日：2018-03-28
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , Christophe Erdmann , John E. McGrath , Bruno Miguel Vaz
IPC: H03M1/10
Abstract: A time-skew adjustment circuit includes an input to receive a series of samples of an input signal from a plurality of channels of an interleaved ADC. A first subtractor calculates distances between consecutive samples in the received series of samples, and a plurality of average circuit code and a plurality of memory banks to calculate a plurality of first average distance, each corresponding to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC. Time-skew detection circuitry calculates respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels. Divergence control circuitry determines an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.
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公开(公告)号：US09680492B1
公开(公告)日：2017-06-13
申请号：US15246369
申请日：2016-08-24
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , Christophe Erdmann
CPC classification number: H03M1/0863 , H03M1/462 , H03M1/468
Abstract: An analog to digital converter (ADC) includes a comparator and a plurality of capacitor pairs coupled between first and second inputs the comparator, where each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage. The ADC also includes a voltage detection circuit and a state machine that is configured to, upon determining during a first cycle that the sampled voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs in a default state such that the sampled analog voltage is unchanged. Otherwise, the state machine is configured to switch the first pair of the plurality of capacitor pairs to change the sampled analog voltage.
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公开(公告)号：US08970419B2
公开(公告)日：2015-03-03
申请号：US13928798
申请日：2013-06-27
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , James Hudner , Ivan Bogue , Declan Carey , Darragh Walsh , Marc Erett
Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.
Abstract translation: 一个模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。
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公开(公告)号：US11709275B2
公开(公告)日：2023-07-25
申请号：US16506064
申请日：2019-07-09
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , John K. Jennings , John G. O′Dwyer
IPC: G01R31/3185 , G01R31/3167 , H03M1/10 , H03K19/173 , G01S19/23
CPC classification number: G01S19/23 , G01R31/3167 , G01R31/318516 , H03K19/1733 , H03M1/1071
Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11563435B2
公开(公告)日：2023-01-24
申请号：US17709167
申请日：2022-03-30
Applicant: XILINX, INC.
Inventor： John Edward McGrath , Woon Wong , John O'Dwyer , Paul Newson , Brendan Farley
IPC: H03K19/1776
Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
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17.发明授权公开(公告)号：US11196423B1
公开(公告)日：2021-12-07
申请号：US16911361
申请日：2020-06-24
Applicant: XILINX, INC.
Inventor： John McGrath , Woon Wong , John O'Dwyer , Paul Newson , Brendan Farley
IPC: H03K19/1776
Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
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公开(公告)号：US11012072B1
公开(公告)日：2021-05-18
申请号：US16749707
申请日：2020-01-22
Applicant: Xilinx, Inc.
Inventor： John K. Jennings , Brendan Farley
IPC: H03K19/003 , H03K19/17704
Abstract: Method and apparatus for monitoring and reconfiguring a programmable device are disclosed. In some implementations, the programmable device may include a processor and a plurality of satellite monitors to determine operating temperatures at various locations throughout the programmable device. When temperatures of at least some of the satellite monitors exceed a threshold, the processor may reconfigure the programmable device using an alternative configuration. The alternative configuration may provide equivalent functionality with respect to an initial configuration through a different arrangement of functional blocks within the programmable device. The new arrangement of functional blocks may reduce operating temperatures by relocating blocks to different regions of the programmable device.
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公开(公告)号：US10862500B1
公开(公告)日：2020-12-08
申请号：US16683731
申请日：2019-11-14
Applicant: Xilinx, Inc.
Inventor： Roberto Pelliconi , Bob Verbruggen , Brendan Farley , Christophe Erdmann
Abstract: Apparatus and associated methods relate to maintaining a total current of a switch cell in a digital-to-analog converter at a controllable operating point by adjusting shunt current control signals applied to programmable shunt current sources in opposite polarity with respect to a tail current control signal applied to a programmable tail current source. In an illustrative example, the total current may flow through differential legs of a switch cell. The programmable shunt current sources may, for example, be configured to compensate for adjustments to the programmable tail current source. In an illustrative example, tail current and shunt currents may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current sources to compensate adjustments to the tail current source may, for example, permit controlled common mode voltage or operating point so as to reduce device voltage stress over a wider dynamic range of output voltages.
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20.发明授权公开(公告)号：US10720926B1
公开(公告)日：2020-07-21
申请号：US16682818
申请日：2019-11-13
Applicant: XILINX, INC.
Inventor： John McGrath , Woon Wong , John O'Dwyer , Paul Newson , Brendan Farley
IPC: H03K19/1776
Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
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