公开(公告)号：US10262911B1

公开(公告)日：2019-04-16

申请号：US15379258

申请日：2016-12-14

Applicant: Xilinx, Inc.

Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

IPC: H01L21/66 ,  H01L23/00

Abstract: A circuit for testing bond connections between a first die and a second die is described. The circuit comprises a defect monitoring circuit implemented on the first die, which is configured as a test die; and a plurality of bond connections between the first die and the second die; wherein the defect monitoring circuit is configured to detect a defect in a bond connection of the plurality of bond connections between the first die and the second die. A method of testing bond connections between a first die and a second die is also described.

公开(公告)号：US09412674B1

公开(公告)日：2016-08-09

申请号：US14062805

申请日：2013-10-24

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Sanjiv Stokes

IPC: H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  G01R31/26

CPC classification number: H01L22/34 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17515 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/1403

Abstract: An integrated circuit includes a die having a conductive layer. The conductive layer includes a data wire, a first power supply wire of a first voltage potential, and a second power supply wire of a second voltage potential different from the first voltage potential. A segment of the data wire is located between, and substantially parallel to, a segment of the first power supply wire and a segment of the second power supply wire. Further, the first power supply wire is coupled to a first probe structure; and, the second power supply wire is coupled to a second probe structure.

Abstract translation: 集成电路包括具有导电层的管芯。 导电层包括数据线，第一电压电位的第一电源线和不同于第一电压电位的第二电压电位的第二电源线。 数据线的一段位于第一电源线的一段和第二电源线的一段之间并基本上平行。 此外，第一电源线耦合到第一探针结构; 并且所述第二电源线耦合到第二探针结构。

公开(公告)号：US09236367B1

公开(公告)日：2016-01-12

申请号：US14625145

申请日：2015-02-18

Applicant: Xilinx, Inc.

Inventor： Cinti X. Chen ,  Myongseob Kim ,  Xiao-Yu Li ,  Mohsen H. Mardi

IPC: H01L27/12 ,  H01L25/00 ,  H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L22/26 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/17 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2223/54493 ,  H01L2224/13124 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/17515 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311

Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.

Abstract translation: 一种用于叠层硅互连技术（SSIT）产品的装置，包括插入器管芯，多个集成电路管芯，在集成电路管芯和内插管芯之间形成有源连接的多个有源部件，以及多个虚设部件 插入器裸片，虚设部件不形成集成电路管芯和内插器管芯之间的有源连接。 虚拟部件的至少一个子集形成图案，并且图案包括插入器裸片的标识符。

公开(公告)号：US11205639B2

公开(公告)日：2021-12-21

申请号：US16798267

申请日：2020-02-21

Applicant: XILINX, INC.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang Whang Chang

IPC: H01L21/50 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

公开(公告)号：US11054461B1

公开(公告)日：2021-07-06

申请号：US16351310

申请日：2019-03-12

Applicant: Xilinx, Inc.

Inventor： Nui Chong ,  Amitava Majumdar ,  Cheang-Whang Chang ,  Henley Liu ,  Myongseob Kim ,  Albert Shih-Huai Lin

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177 ,  H01L25/065

Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

公开(公告)号：US20200303341A1

公开(公告)日：2020-09-24

申请号：US16361617

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

公开(公告)号：US10770430B1

公开(公告)日：2020-09-08

申请号：US16361617

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

公开(公告)号：US10692837B1

公开(公告)日：2020-06-23

申请号：US16041530

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Nui Chong

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.

公开(公告)号：US10431565B1

公开(公告)日：2019-10-01

申请号：US15907034

申请日：2018-02-27

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang

IPC: H01L25/065 ,  H01L23/522 ,  H01L25/00 ,  H01L23/00

Abstract: A stacked wafer assembly and method for fabricating the same are described herein. In one example, a stacked wafer assembly includes a first wafer bonded to a second wafer. The first wafer includes a plurality of fully functional dies and a first partial die formed thereon. The second wafer includes a plurality of fully functional dies and a first partial die formed thereon. Bond pads formed over an inductor of the first partial die of the first wafer are bonded to bond pads formed on the first partial die of the second wafer to establish electrical connection therebetween.