公开(公告)号：US20190096813A1

公开(公告)日：2019-03-28

申请号：US15719288

申请日：2017-09-28

Applicant: Xilinx, Inc.

Inventor： Austin H. Lesea ,  Sundararajarao Mohan ,  Stephen M. Trimberger

IPC: H01L23/538 ,  H01L23/50

CPC classification number: H01L23/5386 ,  G06F15/7892 ,  H01L23/50

Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

公开(公告)号：US20170236809A1

公开(公告)日：2017-08-17

申请号：US15045228

申请日：2016-02-16

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger ,  Mohsen H. Mardi ,  David M. Mahoney

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.

公开(公告)号：US09608827B1

公开(公告)日：2017-03-28

申请号：US14997937

申请日：2016-01-18

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger

IPC: H04L9/32 ,  G11C11/419 ,  G06F21/44 ,  G11C11/41 ,  G06F21/73

CPC classification number: H04L9/3278 ,  G06F21/44 ,  G06F21/73 ,  G09C1/00 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/20 ,  G11C11/41 ,  G11C11/419

Abstract: Circuits and approaches for de-initializing memory circuits. In one implementation, a memory circuit includes a plurality of memory cells. Each memory cell includes a pair of cross-coupled inverters and first and second access transistors coupled to the pair of cross-coupled inverters. A first bit line is coupled to the first access transistor, and a second bit line is coupled to the second access transistor. A de-initialization circuit is coupled to the first and second bit lines. The de-initialization circuit is configured and arranged to equalize signal states on the first and second bit lines in response to a de-initialization signal.

公开(公告)号：US09584329B1

公开(公告)日：2017-02-28

申请号：US14553734

申请日：2014-11-25

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger

IPC: G06F12/14 ,  H04L9/32

CPC classification number: H04L9/3278 ,  H04L2209/34

Abstract: Approaches for using a physically unclonable function (PUF) are described. A selector map is used to indicate stable and unstable bits in a PUF value that is generated by a PUF circuit. The stable bits of the PUF value generated by the PUF circuit may be selected for use by an application, and the unstable bits ignored.

Abstract translation: 描述了使用物理不可克隆功能（PUF）的方法。 选择器图用于指示由PUF电路产生的PUF值中的稳定和不稳定位。 可以选择由PUF电路产生的PUF值的稳定位以供应用使用，并且不稳定位被忽略。

公开(公告)号：US09520949B2

公开(公告)日：2016-12-13

申请号：US14297535

申请日：2014-06-05

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger ,  Austin H. Lesea

IPC: H04B10/548 ,  H04B10/50

CPC classification number: H04B10/503 ,  H04B10/5161 ,  H04B10/548

Abstract: Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations an optical transmitter includes an optical data port configured to engage an optical fiber. The optical transmitter also includes a plurality of lasers coupled to the optical data port and configured and arranged to transmit respective optical signals over the optical fiber via the optical data port when selected. A control circuit of the optical transmitter is configured to receive an input data signal and encode the input data signal for transmission over the optical fiber by selecting one or more of the plurality of lasers at a time. The control circuit is configured to select one or more of the plurality of lasers at a time according to one of a frequency modulation encoding algorithm or an amplitude modulation encoding algorithm.

Abstract translation: 公开了用于光通信的各种装置，电路，系统和方法。 在一些实现中，光发射机包括被配置为接合光纤的光学数据端口。 光发射机还包括耦合到光数据端口的多个激光器，并被配置和布置成当选择时通过光数据端口在光纤上传输相应的光信号。 光发射器的控制电路被配置为接收输入数据信号，并且通过选择一次中的多个激光器中的一个或多个来编码输入数据信号以在光纤上传输。 控制电路被配置为根据频率调制编码算法或幅度调制编码算法之一来一次选择多个激光器中的一个或多个。

公开(公告)号：US09432121B2

公开(公告)日：2016-08-30

申请号：US14297527

申请日：2014-06-05

Applicant: Xilinx, Inc.

Inventor： Austin H. Lesea ,  Stephen M. Trimberger

IPC: H04B10/508 ,  H04B10/50

CPC classification number: H04B10/501 ,  H01L2924/15311 ,  H04B10/503 ,  H04B10/5053 ,  H04B10/508

Abstract: Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes a package substrate and f first interposer mounted on the package substrate. The apparatus also includes a logic circuit and an optical interface circuit connected to the logic circuit via the first interposer. One of the optical interface circuit or the logic circuit is mounted on the first interposer. The optical interface circuit includes a driver circuit configured to receive electronic data signals from the logic circuit. The optical interface circuit also includes an optical transmitter circuit coupled to the driver circuit and configured to output optical data signals encoding the electronic data signals.

Abstract translation: 公开了用于光通信的各种装置，电路，系统和方法。 在一些实施方式中，一种装置包括安装在封装衬底上的封装衬底和f第一插入器。 该装置还包括经由第一插入器连接到逻辑电路的逻辑电路和光接口电路。 光接口电路或逻辑电路中的一个安装在第一插入器上。 光接口电路包括被配置为从逻辑电路接收电子数据信号的驱动器电路。 光接口电路还包括耦合到驱动器电路并被配置为输出编码电子数据信号的光数据信号的光发送器电路。

公开(公告)号：US20160050017A1

公开(公告)日：2016-02-18

申请号：US14459070

申请日：2014-08-13

Applicant: Xilinx, Inc.

Inventor： Austin H. Lesea ,  Stephen M. Trimberger

IPC: H04B10/2507 ,  H04B10/2575

CPC classification number: H04B10/2507 ,  H04B10/07 ,  H04B10/2575 ,  H04B10/58

Abstract: In an adaptation module relating generally to adaptive optical channel compensation, an analysis module is coupled to receive a first data signal and a second data signal and coupled to provide first information and second information. A comparison module is coupled to compare the first information and the second information to provide third information. An adjustment module is coupled to receive the third information to provide fourth information to compensate for distortion in the second data signal with reference to the first data signal. The second data signal is associated with a conversion of the first data signal to an optical signal for communication via an optical channel.

Abstract translation: 在一般涉及自适应光信道补偿的适配模块中，耦合分析模块以接收第一数据信号和第二数据信号，并耦合以提供第一信息和第二信息。 耦合比较模块以比较第一信息和第二信息以提供第三信息。 耦合调整模块以接收第三信息以提供第四信息，以参考第一数据信号补偿第二数据信号中的失真。 第二数据信号与第一数据信号到用于通过光信道的光信号的转换相关联。

公开(公告)号：US20150358084A1

公开(公告)日：2015-12-10

申请号：US14297527

申请日：2014-06-05

Applicant: Xilinx, Inc.

Inventor： Austin H. Lesea ,  Stephen M. Trimberger

IPC: H04B10/50 ,  H04B10/508 ,  H01L25/00

CPC classification number: H04B10/501 ,  H01L2924/15311 ,  H04B10/503 ,  H04B10/5053 ,  H04B10/508

Abstract: Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes a package substrate and f first interposer mounted on the package substrate. The apparatus also includes a logic circuit and an optical interface circuit connected to the logic circuit via the first interposer. One of the optical interface circuit or the logic circuit is mounted on the first interposer. The optical interface circuit includes a driver circuit configured to receive electronic data signals from the logic circuit. The optical interface circuit also includes an optical transmitter circuit coupled to the driver circuit and configured to output optical data signals encoding the electronic data signals.

Abstract translation: 公开了用于光通信的各种装置，电路，系统和方法。 在一些实施方式中，一种装置包括安装在封装衬底上的封装衬底和f第一插入器。 该装置还包括经由第一插入器连接到逻辑电路的逻辑电路和光接口电路。 光接口电路或逻辑电路中的一个安装在第一插入器上。 光接口电路包括被配置为从逻辑电路接收电子数据信号的驱动电路。 光接口电路还包括耦合到驱动器电路并被配置为输出编码电子数据信号的光数据信号的光发送器电路。

公开(公告)号：US09082514B1

公开(公告)日：2015-07-14

申请号：US13867456

申请日：2013-04-22

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger

IPC: H03K19/003 ,  G11C29/52 ,  H04L9/32

CPC classification number: G11C29/06 ,  G11C11/41 ,  G11C2029/4402 ,  H03K19/003 ,  H04L9/3278

Abstract: A method, non-transitory computer readable medium, and apparatus for performing physically unclonable function (PUF) burn-in are disclosed. For example, the method identifies, by a processor, a natural output of an integrated circuit before the integrated circuit is initialized, identifies, by the processor, a physical characteristic of the integrated circuit associated with the physically unclonable function, and ages, by the processor, the physical characteristic of the integrated circuit to burn-in the natural output of the integrated circuit.

Abstract translation: 公开了一种用于执行物理不可克隆功能（PUF）老化的方法，非暂时性计算机可读介质和装置。 例如，该方法由处理器识别在集成电路初始化之前的集成电路的自然输出，由处理器识别与物理不可克隆功能相关联的集成电路的物理特性，并通过 处理器，集成电路的物理特性烧录集成电路的自然输出。

公开(公告)号：US11687108B2

公开(公告)日：2023-06-27

申请号：US17115478

申请日：2020-12-08

Applicant: XILINX, INC.

Inventor： Stephen M. Trimberger

IPC: G05F1/46 ,  G05F1/575

CPC classification number: G05F1/575 ,  G05F1/46

Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.