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    Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
    11.
    发明授权
    Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
    用于集成电路中多级互连的布线结构的双镶嵌结构

    公开(公告)号：US07378740B2

    公开(公告)日：2008-05-27

    申请号：US11196038

    申请日：2005-08-02

    Applicant: Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

    Inventor： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

    Abstract translation: 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

    Method of forming dual damascene structure
    12.
    发明授权
    Method of forming dual damascene structure 有权
    形成双镶嵌结构的方法

    公开(公告)号：US06680248B2

    公开(公告)日：2004-01-20

    申请号：US09991131

    申请日：2001-11-20

    Applicant: Yimin Huang ,  Tri-Rung Yew

    Inventor： Yimin Huang ,  Tri-Rung Yew

    IPC: H01L214763

    CPC classification number: H01L21/76829 ,  H01L21/76807

    Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

    Abstract translation: 形成双镶嵌结构的方法包括以下步骤：提供其上形成有第一导电层的衬底，然后在衬底上顺序形成第一电介质层，抗反射层和第二电介质层。 接下来，对第一电介质层，抗反射层和第二电介质层进行图案化以形成暴露导电层的第一开口。 此后，第二介电层被图案化以在第一导电层上方的位置形成沟槽（或第二开口）。 沟槽和第一开口一起形成双镶嵌结构的开口。 最后，将第二导电材料沉积到开口和沟槽中以形成导电线和双镶嵌结构。

    Method of forming inter-metal interconnection
    14.
    发明授权
    Method of forming inter-metal interconnection 有权
    形成金属间互连的方法

    公开(公告)号：US06352918B1

    公开(公告)日：2002-03-05

    申请号：US09199877

    申请日：1998-11-24

    Applicant: Yimin Huang ,  Chih-Chien Liu ,  Tri-Rung Yew

    Inventor： Yimin Huang ,  Chih-Chien Liu ,  Tri-Rung Yew

    IPC: H01L21311

    CPC classification number: H01L21/76802

    Abstract: A method of forming an inter-metal interconnection is provided. A substrate is provided. A dielectric layer with a metal plug therein is formed on the substrate. An IMD layer is formed on the dielectric layer. An insulating layer and a PE-oxide layer are formed on the IMD layer. A photolithography and etching process is performed to form a trench in the IMD layer and to expose the metal plug in the dielectric layer. A metal is filled into the trench to electrically connect to the metal plug.

    Abstract translation: 提供了形成金属间互连的方法。 提供基板。 在基板上形成有金属塞的电介质层。 在电介质层上形成IMD层。 在IMD层上形成绝缘层和PE-氧化物层。 进行光刻和蚀刻工艺以在IMD层中形成沟槽并露出介电层中的金属插塞。 将金属填充到沟槽中以电连接到金属插头。

    Method of fabricating a copper capping layer
    15.
    发明授权
    Method of fabricating a copper capping layer 有权
    铜覆盖层的制造方法

    公开(公告)号：US06339025B1

    公开(公告)日：2002-01-15

    申请号：US09304436

    申请日：1999-04-03

    Applicant: Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

    Inventor： Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

    IPC: H01L2144

    CPC classification number: H01L21/76886 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867

    Abstract: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

    Abstract translation: 一种制造铜覆盖层的方法。 在暴露的铜层上形成富氮的氮化物层。 由于富含硅的氮化物层内部具有更多的悬空键，富硅氮化物层中的硅容易与铜反应，并且在铜和富硅氮化物层之间形成铜硅化物层。 因此，可以提高铜和富硅氮化物层的粘合性。

    Method of forming bonding pad
    17.
    发明授权
    Method of forming bonding pad 有权
    形成焊盘的方法

    公开(公告)号：US6069066A

    公开(公告)日：2000-05-30

    申请号：US208025

    申请日：1998-12-09

    Applicant: Yimin Huang ,  Tri-Rung Yew

    Inventor： Yimin Huang ,  Tri-Rung Yew

    IPC: H01L21/60 ,  H01L23/485 ,  H01L21/44

    CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14

    Abstract: A method of forming a bonding pad is provided. A substrate is provided and a multi-metal layer is formed on the substrate. An inter-metal dielectric layer with a trench is formed on the multi-metal layer. A conformal barrier layer is formed on the inter-metal dielectric layer. A first metal layer is formed on the barrier layer to fill a part of the trench. A second metal layer is formed on the first metal layer to fill the trench. A part of the first metal layer and a part of the second metal layer flowing out the trench are removed to expose the inter-metal dielectric layer. A cap layer is formed on the inter-metal dielectric layer. A passivation layer is formed on the cap layer. A part of the passivation and a part of the cap layer are removed to form a bonding pad window by a defined masking layer.

    Abstract translation: 提供一种形成接合焊盘的方法。 设置基板，在基板上形成多金属层。 在多金属层上形成具有沟槽的金属间介电层。 在金属间电介质层上形成保形阻挡层。 在阻挡层上形成第一金属层以填充沟槽的一部分。 在第一金属层上形成第二金属层以填充沟槽。 去除第一金属层的一部分和流出沟槽的第二金属层的一部分，以露出金属间介电层。 在金属间介电层上形成盖层。 在盖层上形成钝化层。 通过限定的掩模层去除钝化部分和覆盖层的一部分以形成焊盘窗口。

    Method to fabricate a dual metal-damascene structure in a substrate
    18.
    发明授权
    Method to fabricate a dual metal-damascene structure in a substrate 失效
    在基材中制造双金属镶嵌结构的方法

    公开(公告)号：US06027994A

    公开(公告)日：2000-02-22

    申请号：US102083

    申请日：1998-06-22

    Applicant: Yimin Huang ,  Tri-Rung Yew

    Inventor： Yimin Huang ,  Tri-Rung Yew

    IPC: H01L21/768 ,  H01L23/522 ,  H01L21/4763

    CPC classification number: H01L21/76808 ,  H01L23/5226 ,  H01L2221/1031 ,  H01L2924/0002

    Abstract: A method to fabricate a dual damascene structure in a substrate is disclosed in the present invention. A first silicon oxide layer is deposited over the substrate and a silicon nitride layer is formed on the first silicon oxide layer. The first silicon oxide layer and the silicon nitride layer are etched in order to form a via hole on the substrate. Afterwards, a second silicon oxide layer is deposited to refill into the via hole and to cover the silicon nitride layer. A dry etching process is performed to remove the second silicon oxide layer in the via hole and to form a metal trench in the second silicon oxide layer on the silicon nitride layer and a metal trench in the second silicon oxide layer above the via hole. After the formation of the metal trenches, a portion of the second silicon oxide layer is remained on the sidewalls and the bottom of the via hole. A dry etching process is performed to remove the remaining portion of the second silicon oxide layer. At last, metal material is deposited to refill into the via hole and the metal trench, it is followed by the metal CMP processs to remove the excess metal over the silicon oxide. The dual metal-damascene structure on the substrate is complete.

    Abstract translation: 在本发明中公开了一种在衬底中制造双镶嵌结构的方法。 在衬底上沉积第一氧化硅层，在第一氧化硅层上形成氮化硅层。 蚀刻第一氧化硅层和氮化硅层以在基板上形成通孔。 然后，沉积第二氧化硅层以重新填充到通孔中并覆盖氮化硅层。 进行干蚀刻处理以去除通孔中的第二氧化硅层，并且在氮化硅层上的第二氧化硅层中形成金属沟槽，在通孔上方的第二氧化硅层中形成金属沟槽。 在形成金属沟槽之后，第二氧化硅层的一部分残留在通孔的侧壁和底部。 执行干蚀刻处理以去除第二氧化硅层的剩余部分。 最后，沉积金属材料以再填充到通孔和金属沟槽中，之后是金属CMP工艺以除去氧化硅上的多余金属。 基板上的双金属镶嵌结构完整。

    Multi-strained source/drain structures
    20.
    发明授权
    Multi-strained source/drain structures 有权
    多应变源/漏结构

    公开(公告)号：US08405160B2

    公开(公告)日：2013-03-26

    申请号：US12787972

    申请日：2010-05-26

    Applicant: Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

    Inventor： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

    IPC: H01L27/088 ,  H01L21/8238

    CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

    Abstract translation: 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源极/漏极结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度与第一接近度不同。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

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