公开(公告)号：US20070170549A1

公开(公告)日：2007-07-26

申请号：US11649367

申请日：2007-01-04

申请人： Yukio Tsuzuki ,  Norihito Tokura

发明人： Yukio Tsuzuki ,  Norihito Tokura

IPC分类号： H01L27/082

CPC分类号： H01L27/0664 ,  H01L29/0834 ,  H01L29/7397 ,  H01L29/861

摘要： A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second side of the first layer, a first electrode in a first trench for a gate electrode, a second electrode on the first side N region and in a second trench for an emitter electrode and an anode electrode, and a third electrode on the second side N and P regions for a collector electrode and a cathode. The first trench penetrates the first side N region and the second layer, and reaches the first layer. The second trench penetrates the first side N region, and reaches the second layer.

摘要翻译： 一种半导体器件包括：具有第一面和第二面的衬底; IGBT; 和二极管。 衬底包括第一层，第一层上的第二层，第二层上的第一侧N区，第一层的第二侧上的第二侧N和P区，用于栅极的第一沟槽中的第一电极 电极，第一侧N区域上的第二电极和用于发射电极和阳极电极的第二沟槽中，以及在第二侧的第三电极N和用于集电极和阴极的P区域。 第一沟槽穿过第一侧N区和第二层，并到达第一层。 第二沟槽穿过第一侧N区域并到达第二层。

公开(公告)号：US07692214B2

公开(公告)日：2010-04-06

申请号：US11885334

申请日：2007-03-20

申请人： Norihito Tokura ,  Yukio Tsuzuki ,  Kenji Kouno

发明人： Norihito Tokura ,  Yukio Tsuzuki ,  Kenji Kouno

IPC分类号： H01L29/00

CPC分类号： H01L29/7395 ,  H01L27/0664 ,  H01L29/861

摘要： A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ρ1 and a thickness L1 of the first layer, a resistivity ρ2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (ρ1/ρ2)×(L1·L2/W22)

摘要翻译： 半导体器件包括：半导体衬底; IGBT单元; 和二极管单元。 衬底包括在第一表面上的第一层，相邻地布置在衬底的第二表面上的第二层和第三层以及在第一层和第二层和第三层之间的第四层。 第一层提供了IGBT单元和二极管单元的漂移层。 第二层提供IGBT单元的集电极层。 第三层提供二极管单元的一个电极连接层。 第一层的电阻率和第一层的厚度L1，第四层的电阻率rgr2和厚度L2以及第二层在基板平面上的最小宽度W2的一半具有（＆rgr ; 1 /＆rgr; 2）×（L1·L2 / W22）<1.6。

公开(公告)号：US07586151B2

公开(公告)日：2009-09-08

申请号：US11578949

申请日：2005-05-11

申请人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811

摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.

摘要翻译： 本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。 绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。 半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62。 栅极沟槽21形成为条状，并且端子沟槽62同心地形成。 在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。 也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

公开(公告)号：US6133587A

公开(公告)日：2000-10-17

申请号：US23280

申请日：1998-02-13

申请人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

发明人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/0696

摘要： A n.sup.- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n.sup.+ -type source region 5, which trench 7 passes through the n.sup.+ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n.sup.- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12. A high-reliability gate insulating film 8 is obtained by forming a gate insulating layer on the side walls 7a which surround the island semiconductor region 12.

摘要翻译： n型源极区5形成在半导体衬底4的p型碳化硅半导体层3的表层部分的预定区域上。低电阻p型碳化硅区6形成在 在p型碳化硅半导体层3中的表层部分的预定区域。沟槽7形成在n +型源极区域5中的预定区域中，沟槽7通过n +型源极区域5，并且 p型碳化硅半导体层3，到达n型碳化硅半导体层2.沟槽7具有垂直于半导体衬底4的表面的侧壁7a和平行于半导体衬底的表面的底侧7b 由沟槽7的侧壁7a包围的六边形区域是岛状半导体区域12.通过在侧壁7a上形成栅极绝缘层，形成高可靠性栅极绝缘膜8， 岛半导体区域12。

公开(公告)号：US6133120A

公开(公告)日：2000-10-17

申请号：US704820

申请日：1996-08-28

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Atsuo Fukumoto ,  Hidemitsu Hayashi

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Atsuo Fukumoto ,  Hidemitsu Hayashi

IPC分类号： H01L21/205 ,  C30B25/00 ,  C30B25/02 ,  H01L21/04 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  C01B31/36

CPC分类号： H01L29/7813 ,  C30B25/00 ,  C30B25/02 ,  C30B29/36 ,  H01L21/0455 ,  H01L29/66068 ,  H01L29/1608 ,  Y10S438/931

摘要： A p-type silicon carbide semiconductor having a high carrier concentration and activation rate is provided by doping boron as an acceptor impurity in a single crystal silicon carbide. The boron occupies silicon sites in a crystal lattice of the single crystal silicon carbide.

摘要翻译： 通过在单晶碳化硅中掺杂硼作为受主杂质来提供具有高载流子浓度和活化速率的p型碳化硅半导体。 硼占据单晶碳化硅的晶格中的硅位置。

公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。

公开(公告)号：US5519245A

公开(公告)日：1996-05-21

申请号：US56946

申请日：1993-05-05

申请人： Norihito Tokura ,  Naoto Okabe ,  Naohito Kato

发明人： Norihito Tokura ,  Naoto Okabe ,  Naohito Kato

IPC分类号： H01L29/08 ,  H01L29/739 ,  H01L29/80 ,  H01L23/58 ,  H01L29/76 ,  H01L29/861

CPC分类号： H01L29/0834 ,  H01L29/7395 ,  H01L2924/0002

摘要： An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers. Therefore, the built-in reverse conducting function has a low operating resistance, a large reverse current can be passed, there is no increase in on-resistance, and the turn-off time can be shortened.

摘要翻译： 绝缘栅双极晶体管内置有反向导通功能。 第一导电类型的半导体层形成在漏极侧，在第一导电类型的半导体层上形成用于在载流子注入时引起导电性调制的第二导电类型的半导体层，第二导电类型的半导体层 在与漏电极电连接的第二导电类型的半导体层中形成用于取出与漏电流方向相反的反向导通电流的导通型，并且在第二导电类型的半导体层中形成第二导电类型的半导体层 pn结的附近，赋予和接收载流子以引起电导率调制的pn结附近，杂质浓度高，导致反向导通电流进入不妨碍载流子通过的图案的路径。 因此，内置的反向导通功能具有低的工作电阻，可以通过大的反向电流，导通电阻不增加，并且可以缩短关断时间。

公开(公告)号：US5460985A

公开(公告)日：1995-10-24

申请号：US30338

申请日：1993-03-25

申请人： Norihito Tokura ,  Shigeki Takahashi

发明人： Norihito Tokura ,  Shigeki Takahashi

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8232

CPC分类号： H01L29/0696 ,  H01L21/28167 ,  H01L29/045 ,  H01L29/7813 ,  H01L21/28211 ,  H01L29/4236 ,  Y10S148/116 ,  Y10S148/126

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： PCT No.PCT / JP92 / 00929 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT提交1992年7月22日PCT公布。 公开号WO93 / 03502 日期：1993年2月18日。垂直型功率MOSFET显着降低了其面积的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US4608958A

公开(公告)日：1986-09-02

申请号：US533812

申请日：1983-09-19

申请人： Yasuyuki Sakakibara ,  Norihito Tokura

发明人： Yasuyuki Sakakibara ,  Norihito Tokura

IPC分类号： F02D41/20 ,  F02D41/40 ,  F02P3/08 ,  F02P7/03 ,  F02P15/10

CPC分类号： F02P7/035 ,  F02D41/2096 ,  F02D41/40 ,  F02P15/10 ,  F02P3/0892 ,  F02D2041/2003 ,  Y02T10/44

摘要： A device for driving a load reactance element, such as a piezoelectric actuator for a fuel injection system, including a series reactance element connected in series with the load reactance element, and a resonance circuit formed by the load reactance and the series reactance. First and second switching elements are connected between the resonance circuit and the power source or ground potential. Each of the first and second switching elements is rendered conductive only during a half cycle of resonance. The directions of the load current flowing through the load reactance element are switchable by making alternately the first and second switching elements conductive.

摘要翻译： 用于驱动负载电抗元件的装置，例如用于燃料喷射系统的压电致动器，包括与负载电抗元件串联连接的串联电抗元件，以及由负载电抗和串联电抗形成的谐振电路。 第一和第二开关元件连接在谐振电路和电源或地电位之间。 第一和第二开关元件中的每一个仅在谐振的半周期期间才导通。 流过负载电抗元件的负载电流的方向可以通过交替地使第一和第二开关元件导通来切换。

公开(公告)号：US4584553A

公开(公告)日：1986-04-22

申请号：US617478

申请日：1984-06-05

申请人： Norihito Tokura ,  Hisasi Kawai

发明人： Norihito Tokura ,  Hisasi Kawai

IPC分类号： H01C7/00 ,  H01C17/23 ,  H01C1/01

CPC分类号： H01C17/23

摘要： A coated layer type resistor device having a first resistor element and a second resistor element. The ratio between the resistances of the first and second resistor elements is selected to be greater than a predetermined ratio. The first resistor element is formed on an insulator substrate and consists of a resistor layer and end conductor electrodes at the ends of the resistor layer, while the second resistor element is formed on the substrate and consists of a resistor layer, end conductor electrodes, and a plurality of intermediate conductors. The distance between adjacent ones of the intermediate conductors and the distance between one of the end conductor electrodes and the adjacent intermediate conductor in the second resistor element is equal to the distance between the end conductor electrodes in the first resistor element, so that the temperature coefficient property of the resistance is equal in both the first and second resistor elements.

摘要翻译： 一种具有第一电阻元件和第二电阻元件的涂层型电阻器件。 选择第一和第二电阻元件的电阻之比大于预定的比例。 第一电阻元件形成在绝缘体基板上，由电阻层和电阻层的端部的端部导体电极构成，第二电阻元件形成在基板上，由电阻层，端子导体电极和 多个中间导体。 相邻的中间导体之间的距离和第二电阻元件中的一个端子导体电极与相邻的中间导体之间的距离等于第一电阻元件中端部导体电极之间的距离，使得温度系数 电阻的性质在第一和第二电阻元件两者相等。