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    Nonvolatile semiconductor memory device capable of erasing by a word line unit
    11.
    发明授权
    Nonvolatile semiconductor memory device capable of erasing by a word line unit 失效
    能够通过字线单元擦除的非易失性半导体存储器件

    公开(公告)号：US5402382A

    公开(公告)日：1995-03-28

    申请号：US942887

    申请日：1992-09-10

    申请人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

    发明人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

    IPC分类号： H01L21/8247 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C16/16

    摘要： A nonvolatile semiconductor memory device has a plurality of memory cells, which are arranged in a matrix form having rows and columns and each have floating a gate for holding an information charge, a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a high voltage generator for generating a negative high voltage. The high voltage generator is connected to each word line and has a capacitor to which a predetermined clock is applied in response to a signal for selecting word lines. The semiconductor memory device further comprises an erasing device, which applies the negative high voltage generated by, the high voltage generator to the word line selected by the selection signal in the erasing operation. The erasing device grounds the source line connected to the source of the corresponding memory cell.

    摘要翻译： 非易失性半导体存储器件具有多个存储单元，它们以具有行和列的矩阵形式布置，并且各自具有用于保持信息电荷的栅极，多个位线，多个字线，多个 源极线和用于产生负高电压的高压发生器。 高电压发生器连接到每个字线，并且响应于用于选择字线的信号，具有施加预定时钟的电容器。 半导体存储器件还包括擦除器件，其在擦除操作中将由高电压发生器产生的负高电压施加到由选择信号选择的字线。 擦除装置将连接到相应存储单元的源的源极线接地。

    Internal voltage generator for a non-volatile semiconductor memory device
    12.
    发明授权
    Internal voltage generator for a non-volatile semiconductor memory device 失效
    用于非易失性半导体存储器件的内部电压发生器

    公开(公告)号：US5371705A

    公开(公告)日：1994-12-06

    申请号：US066300

    申请日：1993-05-24

    申请人： Takeshi Nakayama ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Shinichi Kobayashi

    发明人： Takeshi Nakayama ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Shinichi Kobayashi

    IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C17/00 ,  H02M3/07 ,  H03K19/00 ,  G11C7/00

    CPC分类号： G11C5/143 ,  G11C16/12 ,  G11C16/30

    摘要： The semiconductor device includes a voltage generator for generating selectively a signal of a first level or a second level onto a first supply line, and a voltage converter using voltage signals on the first supply line and a second supply line for producing a signal of the voltage level on the first or the second supply line in accordance with an input signal, and a voltage level shifter for detecting the level of the voltage on the first supply line to shift in voltage level a signal on the second power supply line toward the first level when the voltage on the first supply line approaches the first level. The difference of the voltages on the first and second supply lines can be reduced to improve the break-down characteristics of a transistor included in the voltage converter, resulting in a reliable semiconductor device.

    摘要翻译： 半导体器件包括用于在第一电源线上选择性地产生第一电平或第二电平的信号的电压发生器，以及使用第一电源线上的电压信号的电压转换器和用于产生电压信号的第二电源线 根据输入信号在第一或第二供电线上的电平;以及电压电平移位器，用于检测第一电源线上的电压电平，使电压电平将第二电源线上的信号移向第一电平 当第一电源线上的电压接近第一电平时。 可以减小第一和第二电源线上的电压差，以改善包括在电压转换器中的晶体管的分解特性，从而获得可靠的半导体器件。

    Non-volatile semiconductor memory device
    18.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5554868A

    公开(公告)日：1996-09-10

    申请号：US300877

    申请日：1994-09-06

    申请人： Masanori Hayashikoshi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi

    发明人： Masanori Hayashikoshi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/34 ,  H01L29/788

    CPC分类号： G11C16/3404 ,  G11C16/3409

    摘要： There is a case where a memory cell brought to an over-erase (depletion) state if the erasing time is too long, for example, in an electrically erasable non-volatile semiconductor memory device. In this case, the transistor constituting the memory cell is always in ON state and causes erroneous operation. Therefore, it is detected whether there is any memory cell in the over-erase state or not after erasing in each memory cell, and if any memory cell is detected being in the over-erase state, tunnel writing is performed in each memory cell. Specifically, electrons are injected into the floating gate of the transistor constituting each memory cell by a tunnel phenomenon. This causes the memory cell in the over-erase state to recover to a normal state. Detection of the over-erase state and recovery from it are performed by an over-erase correcting circuit 72.

    摘要翻译： 如果擦除时间过长，例如在电可擦除非易失性半导体存储器件中存在存储器单元进入过擦除（耗尽）状态的情况。 在这种情况下，构成存储单元的晶体管总是处于导通状态并导致错误的操作。 因此，在每个存储单元中擦除之后检测是否存在处于过擦除状态的任何存储单元，并且如果检测到任何存储单元处于过擦除状态，则在每个存储单元中进行隧道写入。 具体地，电子通过隧道现象注入构成每个存储单元的晶体管的浮置栅极。 这使得处于过擦除状态的存储单元恢复到正常状态。 通过过擦除校正电路72执行过擦除状态和从其恢复的检测。

    Electrically erasable and programmable non-volatile memory device and a method of operating the same
    19.
    发明授权
    Electrically erasable and programmable non-volatile memory device and a method of operating the same 失效
    电可擦除和可编程的非易失性存储器件及其操作方法

    公开(公告)号：US5428568A

    公开(公告)日：1995-06-27

    申请号：US933436

    申请日：1992-08-20

    申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya

    发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya

    IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C16/3459

    摘要： In a programming mode of operation of a flash type non-volatile semiconductor memory device, an erase voltage pulse is applied a memory cell to bring the memory cell into an erased state. Then, an after-erase writing operation is executed for a memory cell having a threshold voltage lower than a predetermined threshold voltage under the condition of small change in threshold voltage. Alternatively, an erase voltage pulse is applied only to a memory cell having a threshold voltage greater than a predetermined threshold voltage to carry out erasing. Also, after a memory cell is brought to a depletion state by application of an erase voltage pulse, data writing of "0" and "1" is carried out by injection of electrons into the floating gate. The electron injection rate to the floating gate for writing data "0" is set to be greater than that for writing data "1". The state of storing data "1" corresponds to an erase state. According to this scheme, an excessively erased memory cell does not exist and the distribution range of threshold voltage can be reduced. Furthermore, the reprogramming time period for a memory cell data can be carried out in a short time.

    摘要翻译： 在闪存型非易失性半导体存储器件的编程操作模式中，擦除电压脉冲被施加到存储器单元以使存储单元进入擦除状态。 然后，在阈值电压变化小的条件下，对具有低于预定阈值电压的阈值电压的存储单元执行擦除后写入操作。 或者，擦除电压脉冲仅施加到具有大于预定阈值电压的阈值电压的存储器单元以执行擦除。 此外，在通过施加擦除电压脉冲将存储单元置于耗尽状态之后，通过向浮置栅极注入电子来执行“0”和“1”的数据写入。 写入数据“0”的浮动栅极的电子注入速率被设定为大于写入数据“1”的电子注入速率。 存储数据“1”的状态对应于擦除状态。 根据该方案，不存在过度擦除的存储单元，并且可以减小阈值电压的分布范围。 此外，存储单元数据的重新编程时间段可以在短时间内进行。

    Nonvolatile semiconductor memory device and data erasing method thereof
    20.
    发明授权
    Nonvolatile semiconductor memory device and data erasing method thereof 失效
    非易失性半导体存储器件及其数据擦除方法

    公开(公告)号：US5297096A

    公开(公告)日：1994-03-22

    申请号：US711547

    申请日：1991-06-07

    申请人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    发明人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/14 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： G11C16/14 ,  G11C16/16

    摘要： A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.

    摘要翻译： 一种快闪EEPROM，包括分为第一和第二块的存储单元阵列。 为这两个块中的每一个提供擦除用于向存储单元施加擦除脉冲的脉冲施加电路和用于擦除验证存储单元的擦除验证电路。 对应于第一块设置的擦除脉冲施加电路和擦除验证电路与擦除脉冲施加电路和对应于第二块设置的擦除验证电路分开工作。 擦除脉冲施加电路各自由其相应的擦除验证电路控制。 也就是说，每个擦除验证电路仅在检测到相应块中的数据擦除不完整的存储单元时才能使其相应的擦除脉冲施加电路。