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    Semiconductor device
    11.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07859896B2

    公开(公告)日：2010-12-28

    申请号：US12162702

    申请日：2006-02-02

    申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Yoshihisa Fujisaki

    发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Yoshihisa Fujisaki

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/24

    摘要： A semiconductor device for high-speed reading and which has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, information is programmed by a first pulse (reset operation) for programming information flowing in the bit line, a second pulse (set operation) different from the first pulse, and information is read by a third pulse (read operation), such that the current directions of the second pulse and the third pulse are opposite to each other.

    摘要翻译： 提供了一种用于高速读取并具有高数据保持特性的半导体器件。 在包括具有设置在多个字线和多个位线的交叉点的多个存储单元的存储器阵列的半导体器件中，其中每个存储器单元包括信息存储器部分和选择元件，信息由 用于对在位线中流动的信息进行编程的第一脉冲（复位操作），与第一脉冲不同的第二脉冲（设置操作），并且通过第三脉冲（读取操作）读取信息，使得第二脉冲 并且第三脉冲彼此相反。

    Semiconductor storage device
    12.
    发明授权
    Semiconductor storage device 失效
    半导体存储设备

    公开(公告)号：US07864568B2

    公开(公告)日：2011-01-04

    申请号：US12516690

    申请日：2006-12-07

    申请人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

    发明人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

    IPC分类号： G11C11/00

    CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233

    摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.

    摘要翻译： 在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。 半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103， 设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子 连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。

    Semiconductor device and method for manufacturing the same
    15.
    发明授权
    Semiconductor device and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06396092B1

    公开(公告)日：2002-05-28

    申请号：US09381396

    申请日：1999-09-20

    申请人： Shinichiro Takatani ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Kazuyoshi Torii

    发明人： Shinichiro Takatani ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Kazuyoshi Torii

    IPC分类号： H01L2906

    CPC分类号： H01L28/55 ,  H01L28/60

    摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.

    摘要翻译： 半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。 具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。 杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的， 长期可靠性。

    Semiconductor memory and method of manufacturing the same
    19.
    发明授权
    Semiconductor memory and method of manufacturing the same 失效
    半导体存储器及其制造方法

    公开(公告)号：US06309894B1

    公开(公告)日：2001-10-30

    申请号：US09214382

    申请日：1999-01-06

    申请人： Hiroshi Miki ,  Keiko Abdelghafar ,  Yoshihisa Fujisaki

    发明人： Hiroshi Miki ,  Keiko Abdelghafar ,  Yoshihisa Fujisaki

    IPC分类号： H01G706

    CPC分类号： H01L28/56 ,  H01L21/02197 ,  H01L21/02323 ,  H01L21/0234 ,  H01L28/75

    摘要： A semiconductor memory which is improved in reliability by preventing the lowering of capacitance and defective insulation, especially, electrode delamination caused by the formation of the passivation film (insulating film) of a capacitor using a high-dielectric-constant or ferroelectric material by plasma processing at a relatively low temperature and a method for manufacturing the memory. The semiconductor memory has an integrated capacitor composed of a capacitor structure constituted of an upper electrode, a lower electrode, and a capacitor insulating film (of a high-dielectric-constant or ferroelectric thin film) which is held between electrodes and serves as a capacitor insulating film and a protective insulating film which covers the capacitor structure and is formed by plasma treatment. An oxygen introducing layer is further formed on the surface of the thin film constituting the capacitor insulating film. In the manufacturing process of the memory, for example, the oxygen introducing layer is formed on the surface of the high-dielectric-constant or ferroelectric material by introducing oxygen to the boundary between the electrode and the material by conducting heat treatment in an oxygen atmosphere before the protective insulating film (SiO2 passivation film) is formed by plasma treatment after the formation of the electrode. Therefore, lowering of capacitance, defective insulation, and especially, electrode delamination, which are caused by the formation of the passivation film (insulating film), can be prevented.

    摘要翻译： 一种半导体存储器，其通过防止电容降低和绝缘不良，特别是由于通过等离子体处理使用高介电常数或铁电材料的电容器的钝化膜（绝缘膜）形成而导致的电极分层而提高了可靠性 在相对低的温度下和用于制造存储器的方法。 半导体存储器具有由电容器结构构成的集成电容器，该电容器结构由保持在电极之间的上电极，下电极和电容器绝缘膜（高介电常数或铁电薄膜）构成，并用作电容器 绝缘膜和覆盖电容器结构并通过等离子体处理形成的保护绝缘膜。 在构成电容器绝缘膜的薄膜的表面上还形成氧气引入层。 在记忆体的制造过程中，例如，通过在氧气氛中进行热处理，将氧引入电极与材料之间的边界，在高介电常数或铁电体材料的表面上形成氧气导入层 之前，在形成电极之后，通过等离子体处理形成保护绝缘膜（SiO 2钝化膜）。 因此，可以防止由形成钝化膜（绝缘膜）引起的电容降低，绝缘性差，特别是电极分层。

    GaAs single crystal as well as method of producing the same, and semiconductor device utilizing the GaAs single crystal
    20.
    发明授权
    GaAs single crystal as well as method of producing the same, and semiconductor device utilizing the GaAs single crystal 失效
    GaAs单晶及其制造方法以及利用GaAs单晶的半导体器件

    公开(公告)号：US06294804B1

    公开(公告)日：2001-09-25

    申请号：US08943593

    申请日：1997-10-03

    申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

    发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

    IPC分类号： H01L2920

    CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.

    摘要翻译： 通过利用晶片中的晶格畸变分布与场效应晶体管的阈值电压分布之间的强相关性，晶片中晶格畸变的分布减小，从而减轻半导体的特性分布 砷化镓单晶在正常温度下的晶格畸变的最大值和最小值之间的差设定为至多4×10 -5，GaAs单晶中所含的Si原子的密度设定为 最多为1×10 16 cm -3，由此可以使母体为GaAs单晶的半导体元件的特性均匀。