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    MEMORY DEVICE HAVING AN INTEGRATED TWO-TERMINAL CURRENT LIMITING RESISTOR
    12.
    发明申请
    MEMORY DEVICE HAVING AN INTEGRATED TWO-TERMINAL CURRENT LIMITING RESISTOR 有权
    具有集成式两端限流电阻的存储器件

    公开(公告)号：US20130224928A1

    公开(公告)日：2013-08-29

    申请号：US13407359

    申请日：2012-02-28

    申请人： Dipankar Pramanik ,  Tony P. Chiang ,  Mankoo Lee

    发明人： Dipankar Pramanik ,  Tony P. Chiang ,  Mankoo Lee

    IPC分类号： H01L21/02

    CPC分类号： H01L45/14 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

    摘要： A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

    摘要翻译： 提供了并入电阻式开关存储单元或装置中以形成具有改进的器件性能和寿命的存储器件的电阻器结构。 电阻器结构可以是设计成减小流过存储器件的最大电流的两端结构。 还提供了一种用于制造这种存储器件的方法。 该方法包括沉积电阻器结构并沉积存储器件的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联设置以限制存储器件的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器件的开关规范的期望的器件开关电流水平是非常有用的。 存储器件可以形成为可用于各种电子器件的大容量非易失性存储器集成电路的一部分。

    CREATING AN EMBEDDED RERAM MEMORY FROM A HIGH-K METAL GATE TRANSISTOR STRUCTURE
    13.
    发明申请
    CREATING AN EMBEDDED RERAM MEMORY FROM A HIGH-K METAL GATE TRANSISTOR STRUCTURE 有权
    从高K金属栅晶体管结构创建嵌入式RERAM存储器

    公开(公告)号：US20130221317A1

    公开(公告)日：2013-08-29

    申请号：US13407997

    申请日：2012-02-29

    申请人： Dipankar Pramanik ,  Tony P. Chiang ,  David Lazosky

    发明人： Dipankar Pramanik ,  Tony P. Chiang ,  David Lazosky

    IPC分类号： H01L47/00 ,  H01L21/02

    CPC分类号： H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

    摘要： An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

    摘要翻译： 本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极 第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。 第二电极设置在嵌入式电阻式存储单元内靠近第一电极。 第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。 第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

    Method for suppressing lattice defects in a semiconductor substrate
    15.
    发明授权
    Method for suppressing lattice defects in a semiconductor substrate 有权
    抑制半导体衬底中的晶格缺陷的方法

    公开(公告)号：US09472423B2

    公开(公告)日：2016-10-18

    申请号：US11928142

    申请日：2007-10-30

    申请人： Victor Moroz ,  Dipankar Pramanik

    发明人： Victor Moroz ,  Dipankar Pramanik

    IPC分类号： H01L21/324 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/7848

    摘要： A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.

    摘要翻译： 一种用于抑制在晶格中的掺杂剂注入之后的晶格中的渗漏促进缺陷的形成的方法。 该方法提供原子的压缩层，这些原子的尺寸大于晶格构件原子的尺寸。 然后将晶格退火足以使间隙缺陷原子从压缩层发射的时间，并且以这种方式，在离压缩层一定距离处的晶格中形成能量稳定的缺陷。

    Stress-managed revision of integrated circuit layouts
    18.
    发明授权
    Stress-managed revision of integrated circuit layouts 有权
    集成电路布局的压力管理修订

    公开(公告)号：US08069430B2

    公开(公告)日：2011-11-29

    申请号：US12546959

    申请日：2009-08-25

    申请人： Victor Moroz ,  Xi-Wei Lin ,  Dipankar Pramanik

    发明人： Victor Moroz ,  Xi-Wei Lin ,  Dipankar Pramanik

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  H01L21/823807

    摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

    摘要翻译： 大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。 为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。 虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。 沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。 沟槽可以通过用压缩应变材料填充来增加应力。 优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。 优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

    Managing integrated circuit stress using dummy diffusion regions
    19.
    发明授权
    Managing integrated circuit stress using dummy diffusion regions 有权
    使用虚拟扩散区管理集成电路应力

    公开(公告)号：US07897479B2

    公开(公告)日：2011-03-01

    申请号：US12207349

    申请日：2008-09-09

    申请人： Xi-Wei Lin ,  Dipankar Pramanik ,  Victor Moroz

    发明人： Xi-Wei Lin ,  Dipankar Pramanik ,  Victor Moroz

    IPC分类号： H01L21/76 ,  H01L29/00

    CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7846

    摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

    摘要翻译： 大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。 为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。 虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。 沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。 沟槽可以通过用压缩应变材料填充来增加应力。 优选地，虚拟扩散区域和应力松弛沟槽纵向设置在至少N沟道晶体管的沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。 优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

    Filler cells for design optimization in a place-and-route system
    20.
    发明授权
    Filler cells for design optimization in a place-and-route system 有权
    填充单元用于在路线和路径系统中进行设计优化

    公开(公告)号：US07895548B2

    公开(公告)日：2011-02-22

    申请号：US11924738

    申请日：2007-10-26

    申请人： Xi Wei Lin ,  Jyh-Chwen Frank Lee ,  Dipankar Pramanik

    发明人： Xi Wei Lin ,  Jyh-Chwen Frank Lee ,  Dipankar Pramanik

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  G06F17/5068 ,  H01L27/0207

    摘要： A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

    摘要翻译： 提供了一种系统和方法，用于将集成电路设计布置成具有间隙的多个电路布局单元，并且将至少一个子空间中的每个给定的一个插入到依赖于预定数据库的相应填充单元 对所述给定间隙相邻的至少一个电路单元的性能参数产生期望的影响。 电路布局单元可以排成行，并且在一些实施例中，用于给定间隙的适当填充单元的选择取决于与给定间隙相邻的两个电路单元的性能参数所期望的效果。 预定义的填充单元可以包括例如虚拟扩散区域，虚拟多线，N阱边界位移和蚀刻停止层边界移位。 在一个实施例中，可以移动电路布局单元以便容纳选定的填充单元。