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348 条记录 (耗时 0.031 秒)

    Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects
    15.
    发明授权
    Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects 有权
    在Cu大马士革互连中三甲基硅烷气体钝化的SiOC蚀刻的可靠性提高

    公开(公告)号：US07193325B2

    公开(公告)日：2007-03-20

    申请号：US10835788

    申请日：2004-04-30

    申请人： Zhen-Cheng Wu ,  Bi-Troug Chen ,  Weng Chang ,  Syun-Ming Jang ,  Su-Horng Lin

    发明人： Zhen-Cheng Wu ,  Bi-Troug Chen ,  Weng Chang ,  Syun-Ming Jang ,  Su-Horng Lin

    IPC分类号： H01L23/48

    CPC分类号： H01L21/31633 ,  H01L21/02046 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832

    摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.

    摘要翻译： 描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。 具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。 三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。 任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。 然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。 通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。 与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

    Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure
    16.
    发明授权
    Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure 有权
    通过使用新型两步PVD-ALD沉积程序，金属屏障完整性

    公开(公告)号：US07135408B2

    公开(公告)日：2006-11-14

    申请号：US10283862

    申请日：2002-10-30

    申请人： Zhen-Cheng Wu ,  Syun-Ming Jang

    发明人： Zhen-Cheng Wu ,  Syun-Ming Jang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76843

    摘要： A method of forming a barrier layer on the surface of an opening defined in a porous, low dielectric constant (low k), layer, has been developed. The method features the use of a two step deposition procedure using a physical vapor deposition (PVD), procedure to initially deposit a thin underlying, first component of the barrier layer, while an atomic layer deposition (ALD), procedure is then employed for deposition of an overlying second barrier layer component. The underlying, thin barrier layer component obtained via PVD procedures is comprised with the desired properties needed to interface the porous, low k layer, while the overlying barrier layer component obtained via ALD procedures exhibits excellent thickness uniformity.

    摘要翻译： 已经开发了在多孔低介电常数（低k）层限定的开口的表面上形成阻挡层的方法。 该方法的特征在于使用物理气相沉积（PVD）的两步沉积程序，以便首先沉积阻挡层的薄的底层第一部分，同时使用原子层沉积（ALD）方法进行沉积 的上覆第二阻挡层组分。 通过PVD方法获得的底层薄阻挡层组分包含与多孔低k层接合所需的所需性质，而通过ALD方法获得的上覆阻挡层组分表现出优异的厚度均匀性。

    Copper damascene barrier and capping layer
    17.
    发明申请
    Copper damascene barrier and capping layer 审中-公开
    铜镶嵌屏障和封盖层

    公开(公告)号：US20060024954A1

    公开(公告)日：2006-02-02

    申请号：US10910007

    申请日：2004-08-02

    申请人： Zhen-Cheng Wu ,  Lain-Jong Li ,  Yung-Chen Lu ,  Syun-Ming Jang

    发明人： Zhen-Cheng Wu ,  Lain-Jong Li ,  Yung-Chen Lu ,  Syun-Ming Jang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76846

    摘要： A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer; forming an anti-reflectance coating (ARC) layer prior to a photolithographic patterning process; forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer according to said photolithographic patterning and an etching process; blanket depositing a barrier layer including material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening; blanket depositing a refractory metal liner over the barrier layer; blanket depositing at least one metal layer to fill the at least one opening; and, removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.

    摘要翻译： 一种用于形成具有改善的电性能及其结构的镶嵌体的方法，包括提供覆盖在第一蚀刻停止层上的至少一个介电绝缘层; 在光刻图案化工艺之前形成抗反射涂层（ARC）层; 根据所述光刻图案和蚀刻工艺形成至少一个延伸穿过所述至少一个介电绝缘层的厚度部分的开口和第一蚀刻停止层; 覆盖沉积包括选自碳化硅和碳氧化硅的材料的阻挡层，以使所述至少一个开口线对准; 在阻挡层上铺设难熔金属衬垫; 毯子沉积至少一个金属层以填充所述至少一个开口; 以及根据化学机械抛光（CMP）工艺，至少去除覆盖所述至少一个开口水平面的所述至少一个金属层。

    Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects
    18.
    发明申请
    Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects 有权
    在Cu大马士革互连中三甲基硅烷气体钝化的SiOC蚀刻的可靠性提高

    公开(公告)号：US20050245100A1

    公开(公告)日：2005-11-03

    申请号：US10835788

    申请日：2004-04-30

    申请人： Zhen-Cheng Wu ,  Bi-Troug Chen ,  Weng Chang ,  Syun-Ming Jang ,  Su-Horng Lin

    发明人： Zhen-Cheng Wu ,  Bi-Troug Chen ,  Weng Chang ,  Syun-Ming Jang ,  Su-Horng Lin

    IPC分类号： H01L21/306 ,  H01L21/314 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/31633 ,  H01L21/02046 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832

    摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.

    摘要翻译： 描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。 具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。 三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。 任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。 然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。 通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。 与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

    BEOL integration scheme for etching damage free ELK
    19.
    发明申请
    BEOL integration scheme for etching damage free ELK 审中-公开
    BEOL整合方案，用于蚀刻无损ELK

    公开(公告)号：US20060216924A1

    公开(公告)日：2006-09-28

    申请号：US11091307

    申请日：2005-03-28

    申请人： Zhen-Cheng Wu ,  Syun-Ming Jang

    发明人： Zhen-Cheng Wu ,  Syun-Ming Jang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76885 ,  H01L21/7682

    摘要： A preferred embodiment of the invention provides a semiconductor device fabrication method comprising forming a set of interlevel wiring interconnect structures through a low-k dielectric layer, wherein the set comprises a lower wiring level, an upper wiring level, and a conductive via connecting the lower wiring level and the upper wiring level. The method further comprises anisotropically etching the first dielectric layer using the upper wiring level as a mask such that substantially all the first dielectric layer is removed except for a residual dielectric underneath the upper wiring level. A preferred embodiment further comprises removing the residual dielectric with an isotropic etch and then filling substantially all space between adjacent interlevel wiring interconnect structures with a ELK dielectric layer. An alternative embodiment provides a method for forming a dual damascene interconnect structure in an ELK dielectric.

    摘要翻译： 本发明的优选实施例提供一种半导体器件制造方法，包括通过低k电介质层形成一组层间布线互连结构，其中该组包括较低布线电平，上布线电平和连接下部 接线电平和上限线路。 该方法还包括使用上布线电平作为掩模对第一介电层进行各向异性蚀刻，使得基本上所有的第一介电层除去在上布线层以下的残留电介质。 优选实施例还包括用各向同性蚀刻去除残余电介质，然后用​​相邻的层间布线互连结构之间的基本上所有的空间用ELK介电层填充。 另一实施例提供了一种在ELK电介质中形成双镶嵌互连结构的方法。