公开(公告)号：US20220034684A1

公开(公告)日：2022-02-03

申请号：US17075157

申请日：2020-10-20

Applicant: Microchip Technology Inc.

Inventor： Stephane Le Goff ,  Mathieu Sureau ,  Jebas Paul Daniel T ,  Naveen Cannankurichi ,  Subhasis Sasmal ,  Sunny Joel

IPC: G01D5/244 ,  G01B7/00 ,  G01D5/20

Abstract: A system and method for monitoring analog front-end (AFE) circuitry of an inductive position sensor. A redundant AFE channel is provided and alternatively utilized with a sine AFE channel or a cosine AFE channel of the AFE circuitry to obtain a voltage difference that may result in a detection angle error at the electronic control unit (ECU) of the inductive position sensor.

公开(公告)号：US20210373898A1

公开(公告)日：2021-12-02

申请号：US17075493

申请日：2020-10-20

Applicant: Microchip Technology Inc.

Inventor： Pierre Selwan

IPC: G06F9/38 ,  G06F13/20 ,  G06F9/52

Abstract: A system and method for monitoring processors operating in lockstep to detect mismatches in pending pipelined instructions being executed by the processors. A lockstep monitor implemented in hardware is provided to detect the mismatches in the pending pipelined instructions executing on the lockstep processors and to initiate an auto-recovery operation at the processors if a mismatch is detected.

公开(公告)号：US20210173993A1

公开(公告)日：2021-06-10

申请号：US17111218

申请日：2020-12-03

Applicant: Microchip Technology Inc.

Inventor： Madhusudan Raman ,  Nizar Abdallah ,  Julien G. Dunoyer

IPC: G06F30/343 ,  G06N3/08

Abstract: A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.

公开(公告)号：US20210125666A1

公开(公告)日：2021-04-29

申请号：US17140064

申请日：2021-01-02

Applicant: Microchip Technology Inc.

Inventor： Victor Nguyen ,  Fethi Dhaoui ,  John L McCollum ,  Fengliang Xue

IPC: G11C13/00 ,  H01L45/00

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

公开(公告)号：US10756719B2

公开(公告)日：2020-08-25

申请号：US14919000

申请日：2015-10-21

Applicant: Microchip Technology Inc.

Inventor： Isaac Ko ,  Ka Wai Ho ,  Wan Tim Chan ,  Jimes Lei

IPC: H03K17/693 ,  H03K17/06 ,  A61B8/00

Abstract: Described herein are multiple designs for an improved analog switch for use in transmitting high voltage signals without using high voltage power supplies for the switch. The analog switches are able to pass and block input signals in the approximate range of −100V to +100V. The use of translinear loops and a bootstrap configuration results in a constant on-resistance of the symmetrical switches and matches the conductance of each analog switch to the transconductance of an NMOS transistor, which can be easily stabilized with a constant gm biasing scheme. In certain embodiments, a shunt termination (T-switch) configuration is used for better off-isolation, and each of the symmetrical switches has its own translinear loop and thus flexibility of on-resistance and termination voltage.

公开(公告)号：US10199919B2

公开(公告)日：2019-02-05

申请号：US15960930

申请日：2018-04-24

Applicant: Microchip Technology Incorporated

Inventor： David Gammie

IPC: H02M1/38 ,  H02M3/158 ,  H02M1/088 ,  H03K17/567 ,  H03K5/24 ,  H02M3/157 ,  H02M3/156 ,  G05F1/24 ,  H02M1/00

Abstract: A circuit and method for controlling a power converter having a high-side and a low-side switch are provided. The circuit may include a comparator configured to receive a reference voltage at a first input and a ramp voltage at a second output, and to output a delay signal based on a comparison of the reference voltage and the ramp voltage. The delay signal may be configured to turn on one or more of the high-side switch and the low-side switch. The circuit may increase or decrease the reference voltage based on a dead time, which equals an amount of time when the high-side switch and the low-side switch are turned off. The circuit may include a first switch that is controlled to lower the reference voltage if a dead time exceeds a first threshold, and a second switch that is controlled to raise the reference voltage if the dead time delay signal is below a second threshold.

公开(公告)号：US10171072B2

公开(公告)日：2019-01-01

申请号：US15265341

申请日：2016-09-14

Applicant: Microchip Technology Inc.

Inventor： Isaac Ko ,  Ka Wai Ho ,  Wan Tim Chan

IPC: H03K17/687 ,  A61B8/08 ,  H03K17/16 ,  A61B8/00 ,  H03K17/693 ,  H04B1/48

Abstract: An improved analog switch for use in an ultrasound elastography probe is disclosed. The improved analog switch results in less heat dissipation compared to prior art analog switches.

公开(公告)号：US09568597B2

公开(公告)日：2017-02-14

申请号：US13965490

申请日：2013-08-13

Applicant: Microchip Technology Incorporated

Inventor： Benedict Choy ,  Ching Chu ,  Andy Tu

IPC: H03K17/16 ,  G01S7/52

CPC classification number: G01S7/52017

Abstract: An ultrasound image system has a plurality of channels. At least one of the plurality of channels has a capacitive T/R switch.

Abstract translation: 超声图像系统具有多个通道。 多个通道中的至少一个具有电容性T / R开关。

公开(公告)号：US09337725B2

公开(公告)日：2016-05-10

申请号：US13947894

申请日：2013-07-22

Applicant: Microchip Technology, Inc.

Inventor： Alexander Mednik ,  Simon Krugly ,  Marc Tan

IPC: H02J3/12 ,  G05F1/00 ,  H02M3/335 ,  H02M3/156 ,  H02M3/155 ,  H05B33/08

CPC classification number: H02M3/156 ,  H02M3/155 ,  H05B33/0818

Abstract: A switching power converter has an input voltage source. An output load is coupled to the input voltage source. An inductive element is coupled to the load. A switch is coupled to the inductive element. A control circuit is coupled to the switch and the inductive element for activating and deactivating the switch, the control circuit activating and deactivating the switch based on a negative voltage drop across a resistive element of the control circuit.

Abstract translation: 开关电源转换器具有输入电压源。 输出负载耦合到输入电压源。 电感元件耦合到负载。 开关耦合到电感元件。 控制电路耦合到开关和感应元件，用于启动和停用开关，控制电路基于控制电路的电阻元件上的负电压降激活和去激活开关。

公开(公告)号：US09048104B2

公开(公告)日：2015-06-02

申请号：US12834853

申请日：2010-07-12

Applicant: Benedict C. K. Choy ,  Ching Chu ,  Haibing (Robin) Liu ,  Ming-Yuan Yeh

Inventor： Benedict C. K. Choy ,  Ching Chu ,  Haibing (Robin) Liu ,  Ming-Yuan Yeh

IPC: H01L29/40 ,  H01L23/00 ,  H01L23/495 ,  H01L23/525 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0642 ,  H01L23/481 ,  H01L23/49575 ,  H01L23/525 ,  H01L24/06 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7827 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements.

Abstract translation: 电路模块包括具有表面的管芯附接垫和围绕表面的多个引线。 非导电粘合剂在表面上。 多个电子电路管芯在管芯附着垫的表面上。 每个模具具有顶表面和底表面，底表面在粘合剂上。 顶表面具有多个接合焊盘。 第一电子电路管芯具有将第一接合焊盘连接到第二接合焊盘的导电材料的至少一个布线路径。 第一接合线将第二电子电路管芯的接合焊盘连接到第一电子管芯的第一接合焊盘。 第二接合线将第一电子电路管芯的第二接合焊盘连接到引线。 在其中一个裸片包含垂直电路元件的情况下，其中掺杂层沿着该层的底表面形成端子，填充有掺杂多晶硅的沟槽从顶表面延伸到端子以连接至端子。 掺杂多晶硅填充的沟槽还用于隔离和分离不同的电路元件。