公开(公告)号：US20010055242A1

公开(公告)日：2001-12-27

申请号：US09867942

申请日：2001-05-30

Inventor： Ajay Deshmukh ,  Dorian Liepmann

IPC: B01F013/00 ,  B01F015/00

CPC classification number: B01F13/0072 ,  B01F5/0403 ,  B01F13/0093 ,  B01F15/0201 ,  B01F15/024 ,  B01F15/0243 ,  B01F2005/0031 ,  B81C1/00611 ,  B81C2201/0119 ,  Y10T137/0329 ,  Y10T137/2185 ,  Y10T137/2196 ,  Y10T137/2224

Abstract: A micro-electromechanical system and method for continuous laminar fluid mixing. An embodiment of the invention described in the specification includes a mixing channel, a first delivery channel that is connected to the mixing channel, and a second delivery channel that is connected to the mixing channel. A first pump mechanism produces pulses in the first delivery channel. A second pump mechanism produces pulses in the second delivery channel. The first pulsed fluid stream and the second pulsed fluid stream merge in the mixing channel to form a mixed fluid. The pulses in the fluids operate to distort the interface between the fluids to facilitate diffusion between the fluids.

Abstract translation: 一种用于连续层流混合的微机电系统和方法。 在说明书中描述的本发明的实施例包括混合通道，连接到混合通道的第一输送通道和连接到混合通道的第二输送通道。 第一泵机构在第一输送通道中产生脉冲。 第二泵机构在第二输送通道中产生脉冲。 第一脉冲流体流和第二脉冲流体流在混合通道中合并形成混合流体。 流体中的脉冲操作以扭曲流体之间的界面，以促进流体之间的扩散。

公开(公告)号：US08865599B2

公开(公告)日：2014-10-21

申请号：US13672527

申请日：2012-11-08

Applicant: Brewer Science Inc.

Inventor： Dongshun Bai ,  Xie Shao ,  Michelle Fowler ,  Tingji Tang

IPC: H01L21/31 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027 ,  C09D127/18 ,  H01L29/02 ,  B81C1/00 ,  C08L33/16 ,  C08L33/14

CPC classification number: H01L21/31058 ,  B81C1/00611 ,  B81C2201/0119 ,  C08L33/14 ,  C08L33/16 ,  C09D127/18 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/0271 ,  H01L29/02 ,  Y10S438/958

Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.

Abstract translation: 公开了由此形成的平面化方法和微电子结构。 方法和结构使用包含氟化化合物或乙酰乙酰化化合物的平面化材料。 材料是自流平的，并且在不使用蚀刻，接触平面化，化学机械抛光或其它常规平面化技术的情况下实现平面化。

公开(公告)号：US08629011B2

公开(公告)日：2014-01-14

申请号：US13161194

申请日：2011-06-15

Applicant: Brett M. Diamond ,  Franz Laermer ,  Andrew J. Doller ,  Michael J. Daley ,  Phillip Sean Stetson ,  John M. Muza

Inventor： Brett M. Diamond ,  Franz Laermer ,  Andrew J. Doller ,  Michael J. Daley ,  Phillip Sean Stetson ,  John M. Muza

IPC: H01L21/339

CPC classification number: H04R19/005 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C2201/0119 ,  B81C2201/0177 ,  B81C2203/0714 ,  B81C2203/075 ,  B81C2203/0778 ,  H04R19/04 ,  H04R31/00

Abstract: A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer.

Abstract translation: 使用外延生长硅制造麦克风的方法。 提供了一种单片晶圆结构。 该结构的晶片表面包括第一水平区域中的多晶硅和围绕第一水平区域的周边的第二水平区域中的单晶硅。 杂化硅层外延沉积在晶片表面上。 接触多晶硅的混合硅层的部分使用多晶硅作为种子材料，并且接触单晶硅的部分使用单晶硅作为种子材料。 这样，混合硅层在同一晶片结构的相同层中包括单晶硅和多晶硅两者。 然后将CMOS /膜层沉积在混合硅层的顶部。

公开(公告)号：US20120319219A1

公开(公告)日：2012-12-20

申请号：US13161194

申请日：2011-06-15

Applicant: Brett M. Diamond ,  Franz Laermer ,  Andrew J. Doller ,  Michael J. Daley ,  Phillip Sean Stetson ,  John M. Muza

Inventor： Brett M. Diamond ,  Franz Laermer ,  Andrew J. Doller ,  Michael J. Daley ,  Phillip Sean Stetson ,  John M. Muza

IPC: H01L21/20 ,  H01L29/84

CPC classification number: H04R19/005 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C2201/0119 ,  B81C2201/0177 ,  B81C2203/0714 ,  B81C2203/075 ,  B81C2203/0778 ,  H04R19/04 ,  H04R31/00

Abstract: A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer.

Abstract translation: 使用外延生长硅制造麦克风的方法。 提供了一种单片晶圆结构。 该结构的晶片表面包括第一水平区域中的多晶硅和围绕第一水平区域的周边的第二水平区域中的单晶硅。 杂化硅层外延沉积在晶片表面上。 接触多晶硅的混合硅层的部分使用多晶硅作为种子材料，并且接触单晶硅的部分使用单晶硅作为种子材料。 这样，混合硅层在同一晶片结构的相同层中包括单晶硅和多晶硅两者。 然后将CMOS /膜层沉积在混合硅层的顶部。

公开(公告)号：US08203776B2

公开(公告)日：2012-06-19

申请号：US12324259

申请日：2008-11-26

Applicant: Rosemary Urmese Anthraper ,  Lucius M. Sherwin ,  Irma Izzeth Annillo

Inventor： Rosemary Urmese Anthraper ,  Lucius M. Sherwin ,  Irma Izzeth Annillo

IPC: G02B26/08

CPC classification number: G02B26/0833 ,  B81B2201/042 ,  B81B2203/0181 ,  B81C1/00174 ,  B81C1/00611 ,  B81C2201/0119 ,  Y10S359/90

Abstract: A method of forming an electronic device includes providing a patterned lower metal layer over a substrate and a first sacrificial layer there between. A second sacrificial layer is formed over the metal layer, and a portion thereof is removed. A third sacrificial layer is formed over the second sacrificial layer, and an upper metal layer is formed over the third sacrificial layer. A portion of the upper metal layer is removed, and the first, second and third sacrificial layers are removed.

Abstract translation: 形成电子器件的方法包括在衬底之上提供图案化的下金属层和在其之间的第一牺牲层。 第二牺牲层形成在金属层的上方，并且其一部分被去除。 在第二牺牲层上形成第三牺牲层，并且在第三牺牲层上形成上金属层。 除去上部金属层的一部分，并且去除第一，第二和第三牺牲层。

公开(公告)号：US20100128338A1

公开(公告)日：2010-05-27

申请号：US12324259

申请日：2008-11-26

Applicant: Rosemary Urmese Anthraper ,  Lucius M. Sherwin ,  Irma Izzeth Annillo

Inventor： Rosemary Urmese Anthraper ,  Lucius M. Sherwin ,  Irma Izzeth Annillo

IPC: G02B26/08 ,  B29D11/00

CPC classification number: G02B26/0833 ,  B81B2201/042 ,  B81B2203/0181 ,  B81C1/00174 ,  B81C1/00611 ,  B81C2201/0119 ,  Y10S359/90

Abstract: A method of forming an electronic device includes providing a patterned lower metal layer over a substrate and a first sacrificial layer there between. A second sacrificial layer is formed over the metal layer, and a portion thereof is removed. A third sacrificial layer is formed over the second sacrificial layer, and an upper metal layer is formed over the third sacrificial layer. A portion of the upper metal layer is removed, and the first, second and third sacrificial layers are removed.

Abstract translation: 形成电子器件的方法包括在衬底之上提供图案化的下金属层和在其之间的第一牺牲层。 第二牺牲层形成在金属层的上方，并且其一部分被去除。 在第二牺牲层上形成第三牺牲层，并且在第三牺牲层上形成上金属层。 除去上部金属层的一部分，并且去除第一，第二和第三牺牲层。

公开(公告)号：US20060009038A1

公开(公告)日：2006-01-12

申请号：US10889437

申请日：2004-07-12

Applicant: Guy Cohen ,  Steven Cordes ,  Sherif Goma ,  Joanna Rosner ,  Jeannine Trewhella

Inventor： Guy Cohen ,  Steven Cordes ,  Sherif Goma ,  Joanna Rosner ,  Jeannine Trewhella

IPC: H01L21/311 ,  G03C5/00 ,  H01L21/31 ,  H01L21/44 ,  H01L21/302

CPC classification number: H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

公开(公告)号：US09263292B2

公开(公告)日：2016-02-16

申请号：US14097956

申请日：2013-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy M. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

IPC: H01L21/3105 ,  B81C1/00 ,  H01L21/027 ,  H01L21/033 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

公开(公告)号：US20110130005A1

公开(公告)日：2011-06-02

申请号：US13024711

申请日：2011-02-10

Applicant: Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

Inventor： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

IPC: H01L21/3105

CPC classification number: H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract translation: 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。

公开(公告)号：US20090298292A1

公开(公告)日：2009-12-03

申请号：US12538515

申请日：2009-08-10

Applicant: Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

Inventor： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

IPC: H01L21/3105

CPC classification number: H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract translation: 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。