公开(公告)号：US08030730B2

公开(公告)日：2011-10-04

申请号：US12401889

申请日：2009-03-11

Applicant: Tetsuya Nitta ,  Takayuki Igarashi

Inventor： Tetsuya Nitta ,  Takayuki Igarashi

IPC: H01L29/00

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/761 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7317 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/8611

Abstract: An N-layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N-layer, a trench isolation region is formed to surround the N-layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N-layer. Between trench isolation region and the N-layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N-layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

Abstract translation: 在半导体衬底上形成N层，插入BOX层。 在N层中，形成沟槽隔离区以包围作为元件形成区域的N层。 沟槽隔离区形成为从N层的表面到达BOX层。 在沟槽隔离区域和N层之间形成P型扩散区域10a。 连续形成P型扩散区域而不间断地与围绕元件形成区域的沟槽隔离区域的内侧壁的整个表面接触。 在N层的元件形成区域中，形成规定的半导体元件。 因此，形成了可靠地建立电绝缘的半导体器件，而不增加元件形成区域占据的面积。

公开(公告)号：US20110180806A1

公开(公告)日：2011-07-28

申请号：US12946669

申请日：2010-11-15

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L29/7787 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/76281 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/66462

Abstract: A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized.

Abstract translation: 半导体器件的结构和方法包括硅器件层和氮化镓（GaN）器件层。 在一个实施例中，硅器件层和GaN器件层具有彼此共面的上表面。 在另一个实施例中，GaN器件层不直接位于硅器件层之下，并且硅器件层不直接位于GaN器件层的下面。 半导体器件还可以包括形成在硅器件层上和/或内部的硅基半导体器件，以及形成在GaN器件层上和/或内部的氮化物基半导体器件。 GaN器件层可以包括可以形成为保形覆盖层然后平坦化的多个层，或者可以选择性地形成，然后进行平面化。

公开(公告)号：US07588973B2

公开(公告)日：2009-09-15

申请号：US11146002

申请日：2005-06-07

Applicant: Yukihiro Ushiku

Inventor： Yukihiro Ushiku

IPC: H01L21/00 ,  H01L21/8238

CPC classification number: H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/78612 ,  H01L29/78696 ,  H01L29/7881

Abstract: In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

Abstract translation: 在具有多个SOI-Si层的半导体元件的半导体器件中，从半导体衬底的表面的元件隔离区的高度基本相等。 或者，元件隔离区域形成在半导体衬底上相同的高度，然后形成适当地不同厚度的多个SOI-Si层。 以这种方式，可以获得具有与半导体衬底基本相同的高度的元件隔离区域和具有不同高度的SOI-Si层的期望元件区域。 单晶硅膜（SOI-Si层）的厚度可以通过包括沉积非晶硅膜和施加热处理以形成外延层的另一种方法来适当地改变，并且去除不需要的部分。

公开(公告)号：US07586160B2

公开(公告)日：2009-09-08

申请号：US11821977

申请日：2007-06-26

Applicant: Miwa Wake ,  Yoshifumi Yoshida

Inventor： Miwa Wake ,  Yoshifumi Yoshida

IPC: H01L23/62

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624

Abstract: A semiconductor integrated circuit is provided in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Second conductivity type source and drain regions are formed in the semiconductor film. The source region has an ultra-shallow high-density second conductivity type source extension region at a boundary with a channel region, a low-density second conductivity type source extension region under the ultra-shallow high-density second conductivity type source extension region, and a high-density second conductivity type source extension region under the low-density second conductivity type source extension region. The drain region has an ultra-shallow high-density second conductivity type drain extension region at a boundary with the channel region, a low-density second conductivity type drain extension region under the ultra-shallow high-density second conductivity type drain extension region, and a high-density second conductivity type drain extension region under the low-density second conductivity type drain extension region. A gate insulating film is formed on an upper surface of the semiconductor film. A gate electrode is formed on an upper surface of the gate insulating film.

Abstract translation: 提供一种半导体集成电路，其中在通过嵌入式绝缘膜设置在第一导电类型支撑衬底上的第一导电类型半导体膜上形成CMOS晶体管。 在半导体膜中形成第二导电型源区和漏极区。 源极区域在与沟道区域的边界处具有超浅高密度第二导电型源极延伸区域，在超浅高密度第二导电型源极延伸区域下方具有低密度第二导电型源极延伸区域， 以及低密度第二导电型源延伸区域下方的高密度第二导电型源延伸区域。 漏区具有与沟道区边界的超浅高密度第二导电型漏极延伸区，在超浅高密度第二导电型漏极延伸区下方的低密度第二导电型漏极延伸区， 以及低密度第二导电型漏极延伸区域下的高密度第二导电型漏极延伸区域。 在半导体膜的上表面上形成栅极绝缘膜。 栅电极形成在栅极绝缘膜的上表面上。

公开(公告)号：US20090162980A1

公开(公告)日：2009-06-25

申请号：US12354540

申请日：2009-01-15

Applicant: Takashi Ipposhi

Inventor： Takashi Ipposhi

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/7833

Abstract: An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide film is not etched. Next, an N-type impurity is implanted through the oxide film to form source/drain regions in an upper portion of the SOI layer. In this step, adjusting the implantation energy so that the impurity reaches the buried oxide film provides the source/drain regions in contact with the buried oxide film.

Abstract translation: 在SOI层，隔离氧化膜和栅电极上形成氧化膜。 在氧化膜上形成氮化膜。 接下来，仅在氮化膜上进行各向异性蚀刻，以在栅电极的相对侧表面上形成侧壁。 因此，氧化膜不被蚀刻。 接下来，通过氧化膜注入N型杂质，以在SOI层的上部形成源/漏区。 在该步骤中，调整注入能量使得杂质到达掩埋氧化膜，使源/漏区与掩埋氧化膜接触。

公开(公告)号：US07253048B2

公开(公告)日：2007-08-07

申请号：US10766587

申请日：2004-01-28

Applicant: Miwa Wake ,  Yoshifumi Yoshida

Inventor： Miwa Wake ,  Yoshifumi Yoshida

IPC: H01L21/8238

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624

Abstract: A semiconductor integrated circuit has a CMOS transistor formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Thermal oxidation is conducted to form a LOCOS for element separation between transistors in the semiconductor film. A gate oxide film of a second conductivity type transistor is formed over the insulating film. A first conductivity type impurity region is formed between the gate oxide film and the embedded insulating film in a region where the second conductivity type transistor is to be formed. A first conductivity type impurity region having a higher density than that of the first conductivity type impurity region is formed in a middle depth portion of the semiconductor film serving as the proximal region to a drain in the first conductivity type impurity region. A polysilicon film is formed on the gate oxide film and etching the polysilicon film so as to form a gate electrode of the second conductivity type transistor. Ion implantation is performed through the gate electrode so as to form a second conductivity type impurity region in each of a source region and a drain region.

Abstract translation: 半导体集成电路具有形成在通过嵌入绝缘膜设置在第一导电类型支撑衬底上的第一导电类型半导体膜上的CMOS晶体管。 进行热氧化以形成半导体膜中的晶体管之间的元件分离的LOCOS。 在绝缘膜上形成第二导电型晶体管的栅氧化膜。 在要形成第二导电型晶体管的区域中，在栅极氧化膜和嵌入绝缘膜之间形成第一导电型杂质区。 在作为第一导电型杂质区域的漏极的作为近端区域的半导体膜的中间深度部分，形成密度高于第一导电型杂质区的第一导电型杂质区。 在栅氧化膜上形成多晶硅膜，蚀刻多晶硅膜，形成第二导电型晶体管的栅电极。 通过栅电极进行离子注入，以在源极区和漏极区中的每一个中形成第二导电型杂质区。

公开(公告)号：US20060292766A1

公开(公告)日：2006-12-28

申请号：US11458967

申请日：2006-07-20

Applicant: Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

Inventor： Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

IPC: H01L21/84 ,  H01L29/76

CPC classification number: H01L27/10873 ,  H01L21/26506 ,  H01L21/76235 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0214 ,  H01L27/10811 ,  H01L27/10844 ,  H01L27/11521 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/7846

Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

公开(公告)号：US20060273394A1

公开(公告)日：2006-12-07

申请号：US11503156

申请日：2006-08-14

Applicant: Takuji Matsumoto ,  Hirokazu Sayama ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Kazunobu Ota

Inventor： Takuji Matsumoto ,  Hirokazu Sayama ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Kazunobu Ota

IPC: H01L29/78 ,  H01L23/52

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/78615 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).

Abstract translation: 提供一种半导体器件，其通过降低寄生双极晶体管的增益来实现故障的减小和工作特性变化，及其制造方法。 在硅层（3）的上表面上部分地形成氧化硅膜（6）。 多晶硅的栅电极（7）部分地形成在氧化硅膜（6）上。 栅电极（7）下方的氧化硅膜（6）的一部分用作栅极绝缘膜。 在栅极（7）的每个侧表面上形成氮化硅膜（9），其间具有氧化硅膜（8）。 氧化硅膜（8）和氮化硅膜（9）形成在氧化硅膜（6）上。 氧化硅膜（8）在栅极长度方向上的宽度（W1）大于氧化硅膜（6）的厚度（T 1）。

公开(公告)号：US20060170052A1

公开(公告)日：2006-08-03

申请号：US11336874

申请日：2006-01-23

Applicant: Toshiki Kanamoto ,  Masumi Yoshida ,  Tetsuya Watanabe ,  Takashi Ippoushi

Inventor： Toshiki Kanamoto ,  Masumi Yoshida ,  Tetsuya Watanabe ,  Takashi Ippoushi

IPC: H01L27/12

CPC classification number: H01L21/76281 ,  H01L21/761 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203

Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.

Abstract translation: 在与用作PMOS晶体管的漏极区域的P型杂质区域在Y方向上接触的隔离区域中采用FTI结构。 首先，用作体区的第二和第三N型杂质层分别经由第四，第五和第六N型杂质层连接到高电位线，并且还经由第七N型杂质层连接。 第四至第六N型杂质层设置在SOI衬底的绝缘层和PTI区域中的元件隔离绝缘膜之间。

公开(公告)号：US20060068557A1

公开(公告)日：2006-03-30

申请号：US11272342

申请日：2005-11-14

Applicant: Hirosato Ochimizu ,  Yasuyoshi Mishima

Inventor： Hirosato Ochimizu ,  Yasuyoshi Mishima

IPC: H01L21/331

CPC classification number: H01L29/78696 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/78687

Abstract: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34, a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.