公开(公告)号：US5296398A

公开(公告)日：1994-03-22

申请号：US881291

申请日：1992-05-11

申请人： Minoru Noda

发明人： Minoru Noda

IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/336 ,  H01L21/338 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/66878 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/66659

摘要： A field effect transistor having an asymmetric gate includes high dopant concentration source and drain regions. The drain region is shallower and of lower dopant concentration than the source region. The drain is spaced from the gate electrode. Therefore, an ideal FET having a reduced short channel effect and having a lower source resistance and high current drivability (gm) is obtained. When the drain region is produced by ion implantation through a film and the source region is produced by the implantation directly into the substrate, only the drain region is separated from the gate. When the insulating film on the source region is separated from the insulating film on the drain region, the insulating film on the source region is reliably selectively removed, whereby high controllability is obtained.

摘要翻译： 具有不对称栅极的场效应晶体管包括高掺杂浓度源极和漏极区域。 漏极区域比源区域更浅，掺杂浓度低。 漏极与栅电极间隔开。 因此，获得了具有降低的短沟道效应并且具有较低源极电阻和高电流驱动能力（gm）的理想FET。 当通过离子注入通过膜产生漏极区域并且通过直接注入到衬底中产生源极区域时，只有漏极区域与栅极分离。 当源极区域上的绝缘膜与漏极区域上的绝缘膜分离时，源极区域上的绝缘膜被可靠地选择性地去除，从而获得高可控性。

公开(公告)号：US5281839A

公开(公告)日：1994-01-25

申请号：US52856

申请日：1993-04-23

申请人： Bertrand F. Cambou ,  Robert B. Davies

发明人： Bertrand F. Cambou ,  Robert B. Davies

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L29/10 ,  H01L29/812 ,  H01L29/20 ,  H01L29/22

CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L21/28593 ,  H01L29/1029 ,  H01L29/812

摘要： A semiconductor device having a channel region having a first and a second portion. The first and second portions of the channel region are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

摘要翻译： 一种半导体器件，具有具有第一和第二部分的沟道区。 通道区域的第一和第二部分被设计成使得在操作期间只有一小部分被大量耗尽。 因此，制造具有短栅极长度的半导体器件。

公开(公告)号：US5225703A

公开(公告)日：1993-07-06

申请号：US707752

申请日：1991-05-30

申请人： Mitsunori Nakatani

发明人： Mitsunori Nakatani

IPC分类号： H01L21/338 ,  H01L27/095 ,  H01L29/08 ,  H01L29/423 ,  H01L29/812

CPC分类号： H01L29/66878 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/66886 ,  H01L29/8124 ,  Y10S257/90

摘要： A field effect transistor comprises a semi-insulating first compound semiconductor substrate having a surface, a first compound semiconductor active layer disposed at the surface of the substrate and having a first dopant concentration, a gate electrode disposed on the active layer, an epitaxial first compound semiconductor source region disposed on part of the active layer spaced from the gate electrode wherein the source region has a second dopant concentration higher than the first dopant concentration, a source electrode disposed on the source region, an electrically insulating layer disposed on the active layer between the contacting the source region and the gate electrode, a drain region disposed in the substrate adjacent to and in contact with the active layer on an opposite side of the gate electrode from the source region having a dopant concentration intermediate the dopant concentrations of the source region and the active layer, and a drain electrode disposed on the drain region.

公开(公告)号：US5182218A

公开(公告)日：1993-01-26

申请号：US837891

申请日：1992-02-20

申请人： Mitsuaki Fujihira

发明人： Mitsuaki Fujihira

IPC分类号： H01L21/338

CPC分类号： H01L29/66878 ,  Y10S148/10

摘要： The present invention relates to a method of making a compound semiconductor device having a high performance self-aligned LDD structure which has stable characteristics, and is suitable for high integration and high yield, in which after forming a channel layer beneath the substrate surface, using a high performed self-aligned technology, a gate electrode, lightly doped layers and heavily doped layers are formed in predetermined positions by a photolithography for the gate portion. This process of a photolithography is performed only once, therefore, each pattern can be formed with excellent accuracy and reproducibility.

摘要翻译： 本发明涉及一种具有高性能自对准LDD结构的化合物半导体器件的方法，其具有稳定的特性，并且适用于高集成度和高​​产率，其中在衬底表面下形成通道层之后，使用 通过用于栅极部分的光刻法在预定位置形成高执行自对准技术，栅电极，轻掺杂层和重掺杂层。 该光刻的工序仅进行一次，因此，能够以优异的精度和再现性形成各图案。

公开(公告)号：US5043294A

公开(公告)日：1991-08-27

申请号：US574106

申请日：1990-08-29

申请人： Josef Willer ,  Guy Lefranc

发明人： Josef Willer ,  Guy Lefranc

IPC分类号： H01L29/812 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778

CPC分类号： H01L29/66878 ,  H01L21/2815 ,  H01L21/28587 ,  H01L29/42316 ,  Y10S148/14

摘要： A method for manufacturing a field effect transistor having source and drain regions asymmetrically arranged relative to the gate region. A strip-shaped auxiliary layer is applied in the region of the gate. A first and second spacer are laterally fashioned along an auxillary layer, the first spacer is covered with a resist mask and the second spacer is subsequently etched away. The source metallization and the drain metallization are then applied, and a planarizing passivation layer is applied therebetween. This is followed by the application of connecting metallizations for the source, drain and gate regions.

摘要翻译： 一种用于制造场效应晶体管的方法，该场效应晶体管具有相对于栅极区域非对称布置的源区和漏区。 在栅极的区域中施加带状辅助层。 第一和第二间隔物沿着辅助层横向形成，第一间隔物被抗蚀剂掩模覆盖，随后蚀刻掉第二间隔物。 然后施加源极金属化和漏极金属化，并且在其间施加平坦化钝化层。 接下来是应用用于源极，漏极和栅极区域的连接金属化。

公开(公告)号：US4888626A

公开(公告)日：1989-12-19

申请号：US39829

申请日：1987-04-17

申请人： John E. Davey

发明人： John E. Davey

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L29/10 ,  H01L29/812

CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L29/1029 ,  H01L29/8128

摘要： A self-aligned GaAs FET with an active channel which is unaffected by sure charge trapping/emission. The device comprises a channel of n-doped GaAs, a source and drain regions of n.sup.+ GaAs disposed at opposite ends of the channel, a semi-insulating GaAs layer disposed over the channel, with this GaAs layer having open first and second end surfaces disposed at an angle of greater than or equal to 45.degree. relative to the channel plane. A cavity is disposed in the GaAs layer exposing a portion of the channel, and a gate metallization is disposed over the GaAs layer and extending from the first end surface to the second end surface of the GaAs layer and directly contacting the exposed portion of the channel region in the cavity to form a Schottky barrier contact. This gate metallization is not disposed in contact with a significant portion of either of the first and second end surfaces. The ends of the gate metallization overhang slightly the end surfaces of the GaAs layer in order to provide masking to maintain the first and second end surfaces open during fabrication. An insulator such as air may be disposed in contact with these end surfaces.

摘要翻译： 具有不受表面电荷捕获/发射影响的有源沟道的自对准GaAs FET。 该器件包括n掺杂GaAs的沟道，设置在沟道的相对端的n + GaAs的源极和漏极区，设置在沟道上方的半绝缘GaAs层，该GaAs层具有开放的第一和第二端面， 相对于通道平面以大于或等于45°的角度。 在GaAs层中设置一个空腔，暴露出沟道的一部分，栅极金属化层设置在GaAs层上，并从GaAs层的第一端面延伸到第二端面，并直接接触通道的露出部分 区域形成肖特基势垒接触。 该栅极金属化不被设置成与第一和第二端面中的任一个的大部分接触。 栅极金属化的端部略微突出GaAs层的端面，以便提供掩模以在制造期间保持第一和第二端表面打开。 诸如空气的绝缘体可以设置成与这些端面接触。

公开(公告)号：US4849376A

公开(公告)日：1989-07-18

申请号：US137482

申请日：1987-12-23

申请人： Matthew L. Balzan ,  Arthur E. Geissberger ,  Robert A. Sadler

发明人： Matthew L. Balzan ,  Arthur E. Geissberger ,  Robert A. Sadler

IPC分类号： C23F4/00 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/338 ,  H01L21/8252 ,  H01L29/47

CPC分类号： H01L29/66878 ,  H01L21/28581 ,  H01L21/28587 ,  H01L21/32136 ,  H01L21/8252 ,  H01L29/475 ,  Y10S148/051 ,  Y10S148/105 ,  Y10S148/131 ,  Y10S438/945

摘要： A process for manufacturing GaAs FET's having refractory metal gates provides for reducing the size of the gate relative to a mask by an etch sequence which results in precisely controlled and repeatable self-limited undercutting of the mask. A reactive ion etch of the refractory metal in a CF.sub.4 O.sub.2 plasma containing an inert gas provides the self-limiting undercut at a pressure in the range of 175-250 mTorr when the power is less than 0.15 W/cm.sup.2. Preceeding the undercut, an anisotropic RIE in a CF.sub.4 plasma can be employed to clear unmasked areas of the refractory metal and an initial sputter cleaning in argon improves the quality of the initial etch.

摘要翻译： 用于制造具有难熔金属栅极的GaAs FET的工艺提供了通过蚀刻序列来减小栅极相对于掩模的尺寸，这导致了掩模的精确控制和可重复的自限制底切。 含有惰性气体的CF4O2等离子体中的难熔金属的反应离子蚀刻在功率小于0.15W / cm 2时在175-250mTorr的压力下提供自限制底切。 在底切之前，可以使用CF4等离子体中的各向异性RIE来清除难熔金属的未掩蔽区域，并且在氩气中的初始溅射清洗改善了初始蚀刻的质量。

公开(公告)号：US4735913A

公开(公告)日：1988-04-05

申请号：US860139

申请日：1986-05-06

申请人： John R. Hayes

发明人： John R. Hayes

IPC分类号： H01L21/285 ,  H01L21/324 ,  H01L21/338 ,  H01L21/265 ,  H01L21/44

CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L21/3245 ,  Y10S148/105 ,  Y10S148/14 ,  Y10S148/142

摘要： A self-aligned process for fabricating a GaAs semiconductor MESFET by depositing a layer of tungsten over the GaAs substrate, and ion implanting the substrate to provide channel doping. A gate composed of a conductive refractory material is deposited and delineated on the tungsten layer, and source and drain regions are formed in the substrate using the gate as a mask. The resulting device is annealed and contacts are formed to the source and drain regions, and to the gate.

摘要翻译： 用于通过在GaAs衬底上沉积钨层来制造GaAs半导体MESFET的自对准工艺，以及离子注入衬底以提供沟道掺杂。 在钨层上沉积并描绘由导电耐火材料构成的栅极，并且使用栅极作为掩模在基板中形成源区和漏极区。 所得到的器件被退火，并且与源极和漏极区域以及栅极形成接触。

公开(公告)号：US4662060A

公开(公告)日：1987-05-05

申请号：US808916

申请日：1985-12-13

申请人： Olaleye A. Aina ,  Amir A. Lakhani

发明人： Olaleye A. Aina ,  Amir A. Lakhani

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/285 ,  H01L21/338 ,  H01L29/812 ,  H01S5/00 ,  H01L21/283

CPC分类号： H01L29/66863 ,  H01L21/2656 ,  H01L21/28575 ,  H01L21/28581 ,  H01L29/66878 ,  Y10S148/14 ,  Y10S438/951

摘要： A method of forming a semiconductor device having a non-alloyed contact layer. An active region is formed in a substrate and the non-alloyed contact layer is formed in the active region, the barrier height of source and drain electrodes for the non-alloyed contact layer being lower than the barrier height of the source and drain electrodes for the active region or the substrate. The preferred method of forming the non-alloyed contact layer is high dose implantation of an element selected in accordance with the substrate material. For example, if the substrate is GaAs the non-alloyed contact layer is formed by implanting In, and if the substrate is InP the non-alloyed contact layer is formed by implanting As or Sb.

摘要翻译： 一种形成具有非合金接触层的半导体器件的方法。 在基板中形成有源区，在有源区形成非合金化接触层，非合金化接触层的源电极和漏电极的势垒高度低于源极和漏极的势垒高度， 有源区或基底。 形成非合金化接触层的优选方法是根据基材材料选择的元素的高剂量注入。 例如，如果衬底是GaAs，则通过注入In形成非合金接触层，并且如果衬底是InP，则通过注入As或Sb形成非合金接触层。

公开(公告)号：US20150187892A1

公开(公告)日：2015-07-02

申请号：US14416698

申请日：2012-08-03

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Haizhou Yin ,  Keke Zhang

IPC分类号： H01L29/40 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/401 ,  H01L21/76224 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/1029 ,  H01L29/1083 ,  H01L29/41725 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66878 ,  H01L29/78 ,  H01L29/7846 ,  H01L29/812

摘要： A method for manufacturing a semiconductor device is disclosed, comprising: forming a contact sacrificial layer on the substrate, etching the contact sacrificial layer to form a contact sacrificial pattern, wherein the contact sacrificial pattern covers the source region and the drain region and has a gate trench that exposes the substrate; forming a gate spacer and a gate stack structure in the gate trench; partially or completely etching off the contact sacrificial pattern that covers the source region and the drain region so as to form a source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of the double-layer contact sacrificial layer, the method for manufacturing a semiconductor device in accordance with the present invention effectively reduces the spacing between the gate spacer and the contact region and increases the area of contact region, thus effectively reducing the parasitic resistance of the device.

摘要翻译： 公开了一种用于制造半导体器件的方法，包括：在所述衬底上形成接触牺牲层，蚀刻所述接触牺牲层以形成接触牺牲图案，其中所述接触牺牲图案覆盖所述源极区域和所述漏极区域并具有栅极 暴露基板的沟槽; 在所述栅极沟槽中形成栅极间隔物和栅极堆叠结构; 部分地或完全地蚀刻覆盖源极区域和漏极区域的接触牺牲图案，以便形成源极/漏极接触沟槽; 以及在源极/漏极接触沟槽中形成源极/漏极接触。 通过双层接触牺牲层，根据本发明的半导体器件的制造方法有效地减小了栅极间隔物和接触区域之间的间隔并增加了接触区域的面积，从而有效地降低了寄生电阻 的设备。