利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

186 条记录 (耗时 0.019 秒)

    Method and system for reducing the effect of component recovery
    12.
    发明授权
    Method and system for reducing the effect of component recovery 有权
    减少组件回收效果的方法和系统

    公开(公告)号：US09047215B1

    公开(公告)日：2015-06-02

    申请号：US13682727

    申请日：2012-11-20

    申请人： ALTERA Corporation

    发明人： Gordon Chiu ,  Navid Azizi

    IPC分类号： H03M13/00 ,  G06F11/10 ,  H03M13/33 ,  H04L12/70

    CPC分类号： G06F11/108 ,  G06F11/3027 ,  G06F11/3058 ,  G06F11/3093 ,  G06F2201/88 ,  G11C7/1006 ,  H03K17/56 ,  H03K19/01728 ,  H03M13/336 ,  H04L2012/5674

    摘要： Methods, computer-readable mediums and systems for reducing transistor recovery are disclosed. Data which toggles at least one bit may be periodically communicated over a data path, where toggling of at least one bit may effectively reset the recovery period for any transistors in the data path associated with the at least one bit. Timing uncertainty associated with a given transistor may be reduced by limiting the amount of recovery experienced by the transistor. Accordingly, recovery of transistors in a data path may be limited to predetermined amount by toggling bits of the data path at a predetermined frequency, thereby reducing timing uncertainty and allowing a smaller system margin and/or higher data transmission speeds.

    摘要翻译： 公开了用于减少晶体管恢复的方法，计算机可读介质和系统。 切换至少一个位的数据可以通过数据路径周期性地传送，其中至少一个位的切换可以有效地重置与至少一个位相关联的数据路径中的任何晶体管的恢复周期。 通过限制晶体管所经历的恢复量，可以减小给定晶体管的定时不确定性。 因此，可以通过以预定频率切换数据路径的位来将数据路径中的晶体管的恢复限制为预定量，从而减少定时不确定性并允许较小的系统裕度和/或更高的数据传输速度。

    System and method for using pilot signals in non-volatile memory devices
    13.
    发明授权
    System and method for using pilot signals in non-volatile memory devices 有权
    在非易失性存储器件中使用导频信号的系统和方法

    公开(公告)号：US08429488B1

    公开(公告)日：2013-04-23

    申请号：US13480040

    申请日：2012-05-24

    申请人： Xueshi Yang ,  Zining Wu

    发明人： Xueshi Yang ,  Zining Wu

    IPC分类号： H03M13/05 ,  H03M13/33

    CPC分类号： G06F11/1068 ,  G06F11/1012 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2918

    摘要： A memory system including a memory and, to perform a writing operation to store user data among a plurality of cells of the memory, a pilot generator module, a multiplexer module, and a write module. The pilot generator module is configured to randomly alternate between selection of a first scheme by which pilot data is to be stored, along with the user data, among the plurality of cells of the memory, and a second scheme by which the pilot data is to be stored, along with the user data, among the plurality of cells. The pilot data comprises a known predetermined sequence. The multiplexer module is configured to combine the pilot data and the user data in accordance with the selection of the first scheme and the second scheme. The write module is configured to write the pilot data and the user data among the plurality of cells.

    摘要翻译： 一种存储器系统，包括存储器，并且执行写入操作以在存储器的多个单元之间存储用户数据，导频发生器模块，多路复用器模块和写入模块。 导频发生器模块被配置为在存储器的多个小区之间随机选择要存储导频数据的第一方案以及用户数据，以及导频数据到的第二方案 与用户数据一起存储在多个单元中。 导频数据包括已知的预定序列。 复用器模块被配置为根据第一方案和第二方案的选择来组合导频数据和用户数据。 写入模块被配置为在多个单元之间写入导频数据和用户数据。

    METHOD FOR DECODING MULTIWORD INFORMATION
    17.
    发明申请
    METHOD FOR DECODING MULTIWORD INFORMATION 有权
    解密多媒体信息的方法

    公开(公告)号：US20070277080A1

    公开(公告)日：2007-11-29

    申请号：US11837351

    申请日：2007-08-10

    申请人： Wen-Yi Wu ,  Li-Lien Lin ,  Jia-Horng Shieh

    发明人： Wen-Yi Wu ,  Li-Lien Lin ,  Jia-Horng Shieh

    IPC分类号： H03M13/03 ,  H03M13/33

    CPC分类号： G11B20/18 ,  G11B20/1809 ,  G11B2020/1288 ,  G11B2220/2541 ,  H03M13/17 ,  H03M13/27 ,  H03M13/29

    摘要： A method for decoding multiword information comprises steps (a) to (e). In step (a), a multiword information cluster, e.g., ECC, including high protective codewords, e.g., BIS, and low protective codewords, e.g., LDC, is provided. In step (b), the high and low protective codewords are stored into a first memory, e.g., DRAM. In step (c), the high protective codewords are decoded to generate high protective word erasure indicators showing whether decoding errors occur. In step (d), the high protective word erasure indicators are stored into a second memory, e.g., SRAM. In step (e), the low protective codewords are decoded. In the meanwhile, an erasure bit for a low protective codeword is marked by finding high protective codewords close to the low protective codeword in the multiword information cluster and looking up the high protective word erasure indicators of the high protective codewords close to the low protective codeword.

    摘要翻译： 用于解码多字信息的方法包括步骤（a）至（e）。 在步骤（a）中，提供了包括高保护码字（例如BIS）和低保护码字（例如LDC）的多字信息簇，例如ECC。 在步骤（b）中，高和低保护码字被存储到第一存储器，例如DRAM中。 在步骤（c）中，对高保护码字进行解码以产生表示解码错误是否发生的高保护字擦除指示符。 在步骤（d）中，高保护字擦除指示器被存储到第二存储器例如SRAM中。 在步骤（e）中，低保护码字被解码。 同时，通过在多字信息簇中找到靠近低保护码字的高保护码字，并查找靠近低保护码字的高保护码字的高保护字擦除指示符，标记出低保护码字的擦除位 。

    Detecting intermittent losses of synchronization in a fibre channel loop
    18.
    发明授权
    Detecting intermittent losses of synchronization in a fibre channel loop 有权
    检测光纤通道环路间的同步丢失

    公开(公告)号：US07194673B2

    公开(公告)日：2007-03-20

    申请号：US10327338

    申请日：2002-12-20

    申请人： James M. Tuttle ,  Douglas E. Peeke ,  Geoffrey Reid

    发明人： James M. Tuttle ,  Douglas E. Peeke ,  Geoffrey Reid

    IPC分类号： H03M13/33 ,  H03M13/01

    CPC分类号： H04L1/22

    摘要： Described are a storage system and method for detecting an intermittent loss of synchronization in communication signals received by an enclosure connected to a Fibre Channel loop. A control board produces a first signal representing a status of communication signals received by the control board. The first signal is in one of a plurality of logical states. A first logical state indicates that the status of the communication signals is invalid and a second logical state indicates that the status of the communication signals is valid. The control board includes a glitch-detection circuit that places a second signal in an asserted logical state when the first signal is in the first logical state during a time interval and holds the second signal at the asserted logical state when the first signal transitions from being in the first logical state to being in the second logical state during the time interval.

    摘要翻译： 描述了一种用于检测由连接到光纤通道环路的外壳接收的通信信号中的间歇性同步丢失的存储系统和方法。 控制板产生表示由控制板接收的通信信号的状态的第一信号。 第一信号是多个逻辑状态之一。 第一逻辑状态表示通信信号的状态无效，第二逻辑状态表示通信信号的状态有效。 控制板包括毛刺检测电路，当第一信号在时间间隔期间处于第一逻辑状态时，将第二信号置于有效逻辑状态，并且当第一信号从第 处于处于第二逻辑状态的第一逻辑状态。

    Self orthogonal decoding circuit and self orthogonal decoding method
    20.
    发明授权
    Self orthogonal decoding circuit and self orthogonal decoding method 有权
    自正交解码电路和自正交解码方法

    公开(公告)号：US06944805B2

    公开(公告)日：2005-09-13

    申请号：US09964195

    申请日：2001-09-26

    申请人： Katsutoshi Seki

    发明人： Katsutoshi Seki

    IPC分类号： G06F11/10 ,  H03M13/23 ,  H03M13/33 ,  H03M13/39

    CPC分类号： H03M13/33 ,  H03M13/23

    摘要： A self orthogonal decoding circuit and a method thereof, can be realized with simple circuit construction and can significantly improve error correction performance. The self orthogonal decoding circuit performing decoding for self orthogonal code repeats decoding for the self orthogonal code for a plurality of times.

    摘要翻译： 可以通过简单的电路结构实现自正交解码电路及其方法，可以显着提高纠错性能。 执行自正交码的解码的自正交解码电路重复对于自正交码多次的解码。