公开(公告)号：US11239205B2

公开(公告)日：2022-02-01

申请号：US16741003

申请日：2020-01-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chia Hu ,  Ming-Fa Chen

IPC分类号： H01L25/065 ,  H01L25/03 ,  H01L25/18 ,  H01L23/552 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

摘要： A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

公开(公告)号：US11056373B2

公开(公告)日：2021-07-06

申请号：US14918189

申请日：2015-10-20

申请人： Apple Inc.

发明人： Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L25/03 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498

摘要： Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

公开(公告)号：US11018026B2

公开(公告)日：2021-05-25

申请号：US16699283

申请日：2019-11-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC分类号： H05K1/11 ,  H05K1/18 ,  H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H05K1/14

摘要： A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.

公开(公告)号：US10854568B2

公开(公告)日：2020-12-01

申请号：US15647704

申请日：2017-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L23/538 ,  H01L25/03 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H01L25/18

摘要： A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

公开(公告)号：US10734367B2

公开(公告)日：2020-08-04

申请号：US16232159

申请日：2018-12-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L25/03 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

摘要： A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

公开(公告)号：US10679955B2

公开(公告)日：2020-06-09

申请号：US15788189

申请日：2017-10-19

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Tae Hyun Kim ,  Thomas A. Kim ,  Kyu Bum Han

IPC分类号： H01L23/367 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L23/552 ,  H01L25/03

摘要： A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.

公开(公告)号：US10651050B2

公开(公告)日：2020-05-12

申请号：US16418091

申请日：2019-05-21

申请人： Micron Technology, Inc.

发明人： Eiichi Nakano

IPC分类号： H01L21/66 ,  H01L21/447 ,  H01L21/687 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03

摘要： Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.

公开(公告)号：US10600713B2

公开(公告)日：2020-03-24

申请号：US15979752

申请日：2018-05-15

申请人： SK hynix Inc.

发明人： Min Kyu Kang ,  Jae Hyun Son ,  Ji Hyeok Shin

IPC分类号： H01L23/34 ,  H01L23/367 ,  H01L25/065 ,  H01L23/31 ,  H01L25/18 ,  H01L25/03 ,  H01L23/373 ,  H01L23/433 ,  H01L23/16

摘要： A semiconductor package includes a first semiconductor chip and a second semiconductor chip which are disposed side-by-side on a surface of a package substrate. A heat insulation wall is disposed between the first semiconductor chip and the second semiconductor chip. The heat insulation wall thermally isolates the first semiconductor chip from the second semiconductor chip.

公开(公告)号：US10553774B2

公开(公告)日：2020-02-04

申请号：US15999006

申请日：2018-08-20

申请人： FACE INTERNATIONAL CORPORATION

发明人： Clark D. Boyd

IPC分类号： H01L35/32 ,  H01L35/34 ,  H01L35/02 ,  H01L25/03

摘要： A method for forming a unique, environmentally-friendly energy harvesting element is provided. A configuration of the energy harvesting element causes the energy harvesting element to autonomously generate renewable energy for use in electronic systems, electronic devices and electronic system components. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured in a manner to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. An energy harvesting component is also provided that includes a plurality of energy harvesting elements electrically connected to one another to increase a power output of the electric harvesting component.

公开(公告)号：US20190252329A1

公开(公告)日：2019-08-15

申请号：US16392815

申请日：2019-04-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC分类号： H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L25/03

CPC分类号： H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

摘要： Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.