公开(公告)号：US20100050939A1

公开(公告)日：2010-03-04

申请号：US12198326

申请日：2008-08-26

Applicant: YU PIN HSU ,  YUAN MING CHANG ,  WEI HENG LEE ,  CHENG DA WU

Inventor： YU PIN HSU ,  YUAN MING CHANG ,  WEI HENG LEE ,  CHENG DA WU

IPC: B05C11/00

CPC classification number: H01L21/67253

Abstract: A method for determining the performance of an implanting apparatus comprises the steps of forming a dopant barrier layer on a substrate, forming a target layer on the dopant barrier layer, performing an implanting process by using the implanting apparatus to implant dopants into the target layer such that the target layer becomes conductive, measuring at least one electrical property of the target layer, and determining the performance of the implanting apparatus by taking the electrical property into consideration. In one embodiment of the present invention, the dopant barrier layer is silicon nitride layer, the target layer is a polysilicon layer, and the electrical property is the sheet resistance of the conductive polysilicon layer.

Abstract translation: 一种用于确定植入装置的性能的方法包括以下步骤：在衬底上形成掺杂剂阻挡层，在掺杂剂阻挡层上形成目标层，通过使用注入装置将掺杂剂注入目标层，执行注入过程， 目标层变得导电，测量目标层的至少一个电性质，以及通过考虑电性能来确定植入装置的性能。 在本发明的一个实施例中，掺杂剂阻挡层是氮化硅层，目标层是多晶硅层，电性能是导电多晶硅层的薄层电阻。

公开(公告)号：US20100019309A1

公开(公告)日：2010-01-28

申请号：US12178465

申请日：2008-07-23

Applicant: LIH WEI LIN ,  WEI SHENG HSU

Inventor： LIH WEI LIN ,  WEI SHENG HSU

IPC: H01L29/792

CPC classification number: H01L29/7923 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887

Abstract: A multi-level flash memory structure comprises a semiconductor substrate having a protrusion, a plurality of storage structures separated by the protrusion, a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, a gate structure positioned on the dielectric layer, and several diffusion regions positioned at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate.

Abstract translation: 多级闪速存储器结构包括具有突起的半导体衬底，由突起分开的多个存储结构，覆盖存储结构的覆盖层和半导体衬底的突起，位于介电层上的栅极结构，以及 几个扩散区域位于突起的侧面。 每个存储结构包括电荷捕获位点和将电荷捕获位点与半导体衬底隔离的绝缘结构。

公开(公告)号：US20100006814A1

公开(公告)日：2010-01-14

申请号：US12172162

申请日：2008-07-11

Applicant: Frederick T. Chen ,  Ming-Jinn Tsai

Inventor： Frederick T. Chen ,  Ming-Jinn Tsai

IPC: H01L47/00 ,  H01L21/06

CPC classification number: H01L45/144 ,  H01L45/06 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1691

Abstract: A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer.

Abstract translation: 提出了相变存储单元。 相变存储器包括底部电极; 形成为与底部电极接触的相变间隔件; 导电层，其具有垂直部分和水平部分，其中所述导电层经由所述水平部分电连接到所述相变间隔件; 以及通过导电层的垂直部分与导电层电连接的顶部电极。

公开(公告)号：US20100001394A1

公开(公告)日：2010-01-07

申请号：US12167703

申请日：2008-07-03

Applicant: LI PENG CHANG ,  JUNG CHUN LIN

Inventor： LI PENG CHANG ,  JUNG CHUN LIN

IPC: H01L23/04

CPC classification number: H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced.

Abstract translation: 芯片封装包括半导体芯片，耦合到半导体芯片的多个引脚以及被配置为在引脚之间形成电连接的导电结构，其中电连接被配置为当芯片封装插入插座时被禁用 。 由于引脚通过导电结构电连接，因ESD事件发生时，由ESD事件引起的浪涌电流可分配给所有引脚而不是单引脚。 因此，连接到引脚的所有ESD保护电路可用于在ESD事件期间耗散浪涌电流，并且可以显着降低由ESD引起的电路损坏。

公开(公告)号：US07638442B2

公开(公告)日：2009-12-29

申请号：US12149906

申请日：2008-05-09

Applicant: Cheng-Ta Wu ,  Da-Yu Chuang ,  Yen-Da Chen ,  Lihan Lin

Inventor： Cheng-Ta Wu ,  Da-Yu Chuang ,  Yen-Da Chen ,  Lihan Lin

IPC: H01L21/00

CPC classification number: H01L21/28202 ,  H01L21/28185

Abstract: A process for forming a silicon nitride layer on a gate oxide film as part of formation of a gate structure in a semiconductor device includes: forming a layer of silicon nitride on top of a gate oxide film on a semiconductor substrate by a nitridation process, heating the semiconductor substrate in an annealing chamber, exposing the semiconductor substrate to N2 in the annealing chamber, and exposing the semiconductor substrate to a mixture of N2 and N2O in the annealing chamber.

Abstract translation: 在半导体器件中形成栅极结构的一部分，在栅极氧化膜上形成氮化硅层的工艺包括：通过氮化工艺在半导体衬底上的栅极氧化膜的顶部上形成氮化硅层，加热 在退火室中的半导体衬底，将半导体衬底暴露于退火室中的N2，并将半导体衬底暴露于退火室中的N 2和N 2 O的混合物。

公开(公告)号：US20090317982A1

公开(公告)日：2009-12-24

申请号：US12142414

申请日：2008-06-19

Applicant: Ming Yen Li ,  Hsiao Che Wu ,  De Long Chen ,  Wen Li Tsai

Inventor： Ming Yen Li ,  Hsiao Che Wu ,  De Long Chen ,  Wen Li Tsai

IPC: H01L21/31 ,  C23C16/00

CPC classification number: H01L21/0228 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45544 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/31604

Abstract: An atomic layer deposition apparatus comprises a reaction chamber, a heater configured to heat a semiconductor wafer positioned on the heater, an oxidant supply configured to deliver oxidant-containing precursors having different oxidant concentrations to the reaction chamber, and a metal supply configured to deliver a metal-containing precursor to the reaction chamber. The present application also discloses a method for preparing a dielectric structure comprising the steps of placing a substrate in a reaction chamber, performing a first atomic layer deposition process including feeding an oxidant-containing precursor having a relatively lower oxidant concentration and a metal-containing precursor to form an thinner interfacial layer on the substrate, and performing a second atomic layer deposition process including feeding the oxidant-containing precursor having an oxidant concentration higher than that used to grow the first metal oxide layer and the metal-containing precursor into the reaction chamber.

Abstract translation: 原子层沉积装置包括反应室，被配置为加热位于加热器上的半导体晶片的加热器，被配置为将具有不同氧化剂浓度的含氧化剂的前体输送到反应室的氧化剂供应源，以及被配置为输送 含金属的前体到反应室。 本申请还公开了一种制备电介质结构的方法，包括以下步骤：将基底放置在反应室中，执行第一原子层沉积工艺，包括进料含氧化剂浓度较低的含氧化剂的前体和含金属的前体 在衬底上形成较薄的界面层，并且执行第二原子层沉积工艺，包括将氧化剂浓度高于用于将第一金属氧化物层和含金属的前体生长的氧化剂浓度进料到反应室中 。

公开(公告)号：US20090303817A1

公开(公告)日：2009-12-10

申请号：US12173823

申请日：2008-07-16

Applicant: Chung-Yuan Chang ,  Ming Hsieh Tsai ,  Che-Yi Hsu ,  Yuan-Hwa Lee

Inventor： Chung-Yuan Chang ,  Ming Hsieh Tsai ,  Che-Yi Hsu ,  Yuan-Hwa Lee

IPC: G11C29/04

CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C29/025 ,  G11C29/50016 ,  G11C2029/1202

Abstract: A leakage testing method for a DRAM having a recess gate is provided. The method includes the steps of: programming to set the first storage unit and the second storage unit of a same memory cell with different storage statuses; and disturbing one of the word lines extending through the memory cells; then determining whether the DRAM is acceptable or not. When another one of the word lines extending through the memory cells is caused with a reading error by disturbing the one of the word lines extending through the memory cells, a failure is determined as occurred, and the failure is attributed to a leakage type of extended depletion region. When the another one of the word lines extending through the memory cells is not caused with a reading error by disturbing the one of the word lines extending through the memory cells, the DRAM is determined as acceptable.

Abstract translation: 提供了具有凹槽的DRAM的漏电检测方法。 该方法包括以下步骤：对具有不同存储状态的相同存储单元的第一存储单元和第二存储单元进行编程; 并扰乱延伸通过存储器单元的字线之一; 然后确定DRAM是否可接受。 当延伸通过存储单元的另一个字线通过干扰延伸通过存储器单元的字线之一而引起读取误差时，确定发生故障，并且故障归因于扩展的泄漏类型 耗尽区。 当延伸通过存储单元的字线中的另一条字线不是通过干扰延伸通过存储单元的字线之一而引起读取误差时，DRAM被确定为可接受的。

公开(公告)号：US20090294750A1

公开(公告)日：2009-12-03

申请号：US12325067

申请日：2008-11-28

Applicant: Jen-Chi Chuang ,  Yung-Fa Lin ,  Ming-Jeng Huang

Inventor： Jen-Chi Chuang ,  Yung-Fa Lin ,  Ming-Jeng Huang

IPC: H01L45/00

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/148 ,  H01L45/1691

Abstract: An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively.

Abstract translation: 提供了一种示例性相变存储器件，包括其上形成有第一电极的衬底。 第一电介质层形成在第一电极和衬底之上。 多个杯形加热电极分别设置在第一电介质层的一部分中。 在第一电介质层上形成第一绝缘层，部分覆盖杯形加热电极和第一绝缘层之间的第一介电层。 在第一电介质层上形成第二绝缘层，部分覆盖杯形加热电极和第一绝缘层之间的第一介电层。 一对相变材料层分别设置在第二绝缘层的相对的侧壁上并与杯形加热电极之一接触。 一对第一导电层分别沿第二方向形成在第二绝缘层上。

公开(公告)号：US20090283822A1

公开(公告)日：2009-11-19

申请号：US12122150

申请日：2008-05-16

Applicant: WAN TENG HSIEH ,  I HSUAN LIAO ,  SHIH FANG CHEN ,  TING CHANG CHANG ,  PENG BO XI ,  WEI REN CHEN

Inventor： WAN TENG HSIEH ,  I HSUAN LIAO ,  SHIH FANG CHEN ,  TING CHANG CHANG ,  PENG BO XI ,  WEI REN CHEN

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L29/7881 ,  H01L29/42332

Abstract: A non-volatile memory structure includes a substrate having two doped regions, a charge-trapping structure positioned substantially between the two doped regions, and a conductive structure positioned on the charge-trapping structure, wherein the charge-trapping structure includes a silicon-oxy-nitride layer and metallic nano-dots embedded in the silicon-oxy-nitride layer. The non-volatile memory structure formed by performing a first thermal oxidation process to form a high-k dielectric layer on a substrate, forming a metal-containing semiconductor layer including silicon or germanium on the high-k dielectric layer, forming a silicon layer on the metal-containing semiconductor layer, and performing a second thermal oxidation process to convert the metal-containing semiconductor layer to a silicon-oxy-nitride layer with embedded metallic nano-dots, wherein at least one of the first thermal oxidation process and the second thermal oxidation process is performed in a nitrogen-containing atmosphere.

Abstract translation: 非易失性存储器结构包括具有两个掺杂区域的基底，基本上位于两个掺杂区域之间的电荷俘获结构，以及位于电荷俘获结构上的导电结构，其中电荷俘获结构包括硅 - 氧 氮化物层和嵌入在硅 - 氮化物层中的金属纳米点。 通过进行第一热氧化处理以在衬底上形成高k电介质层而形成的非易失性存储结构，在高k电介质层上形成包含硅或锗的含金属的半导体层，形成硅层 所述含金属的半导体层，并且进行第二热氧化工艺以将含金属的半导体层转换成具有嵌入的金属纳米点的硅 - 氮化物层，其中所述第一热氧化工艺和所述第二热氧化工艺中的至少一个 在含氮气氛中进行热氧化处理。

公开(公告)号：US20090276750A1

公开(公告)日：2009-11-05

申请号：US12198121

申请日：2008-08-26

Applicant: Chun-Yu Lin ,  Chia-Jung Liou ,  Cheng-Hung Ku ,  Feng-Yuan Chiu ,  Chun-Kuang Lin ,  Chih-Chiang Huang

Inventor： Chun-Yu Lin ,  Chia-Jung Liou ,  Cheng-Hung Ku ,  Feng-Yuan Chiu ,  Chun-Kuang Lin ,  Chih-Chiang Huang

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/68

Abstract: A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.

Abstract translation: 提供了一种用于建立用于制造器件的掩模图案的散射线规则的方法。 该方法描述如下。 首先，根据掩模图案建立至少一个图像模拟模型，以及基于掩模图案用于制造该装置的工艺参考组。 接下来，将多个散射条参考集合应用于图像模拟模型，以分别生成多个模拟图像。 此外，根据筛选标准，将模拟图像的一部分选择为多个候选布局。 接下来，根据选择规则将候选布局之一确定为图案布局，并且将与图案布局相对应的散射条参考集确定为掩模图案的散射条规则。