公开(公告)号：US11874774B2

公开(公告)日：2024-01-16

申请号：US17031834

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Ganesh Balakrishnan ,  Joe Sargunaraj ,  Chintan S. Patel ,  Girish Balaiah Aswathaiya ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F12/0891 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084

CPC classification number: G06F12/0891 ,  G06F9/467 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/0833

Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

公开(公告)号：US20240012970A1

公开(公告)日：2024-01-11

申请号：US17861623

申请日：2022-07-11

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： David Akselrod ,  Alexander Kaganov ,  David M. Dahle ,  Tyrone Huang

IPC: G06F30/3308

CPC classification number: G06F30/3308 ,  G06F2119/18

Abstract: Techniques for implementing an overstress design for verification that reduce production and verification time by enabling a verification system to perform verification of components of a circuit design selectively, accurately, and exhaustively under extreme stress scenarios are disclosed. Circuit nodes in an emulation model are selected and overstress is provided to the nodes such that behavior of the circuit under such extreme stress scenarios is readily observable, enabling designers to produce circuits that are more secure, reliable, and resilient in case of failures. Overstress is provided to the node to enable verification of the emulation model without having to design complex test signal representations to produce extreme stress conditions. A request for manufacture is generated including aspects of the emulation model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the emulation model.

公开(公告)号：US11869874B2

公开(公告)日：2024-01-09

申请号：US17121039

申请日：2020-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Wuu ,  David Johnson

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H02M3/04 ,  H03K19/20

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H02M3/04 ,  H03K19/20 ,  H01L2224/08146 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: A stacked die system includes at least three dies. A first die has a same design as a second die. The first die includes a first circuit, and the second die includes a corresponding second circuit. A signal is received at the first die and sent to the third die via the second die. The signal is routed through either the first circuit or the second circuit but not both. Accordingly, an operation is performed on the signal prior to the signal reaching the third die but the operation is not performed by both the first circuit and the second circuit.

公开(公告)号：US11868818B2

公开(公告)日：2024-01-09

申请号：US15273304

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory W. Smaus ,  John M. King ,  Matthew A. Rafacz ,  Matthew M. Crum

IPC: G06F9/52 ,  G06F9/50

CPC classification number: G06F9/52 ,  G06F9/50

Abstract: Techniques for selectively executing a lock instruction speculatively or non-speculatively based on lock address prediction and/or temporal lock prediction. including methods an devices for locking an entry in a memory device. In some techniques, a lock instruction executed by a thread for a particular memory entry of a memory device is detected. Whether contention occurred for the particular memory entry during an earlier speculative lock is detected on a condition that the lock instruction comprises a speculative lock instruction. The lock is executed non-speculatively if contention occurred for the particular memory entry during an earlier speculative lock. The lock is executed speculatively if contention did not occur for the particular memory entry during an earlier speculative lock.

公开(公告)号：US20240005971A1

公开(公告)日：2024-01-04

申请号：US17853418

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/109

Abstract: An arbiter is operable to pick commands from a command queue for dispatch to a memory. The arbiter includes a traffic throttle circuit for mitigating excess power usage increases in coordination with one or more additional arbiters. The traffic throttle circuit includes a monitoring circuit and a throttle circuit. The monitoring circuit is for measuring a number of read and write commands picked by the arbiter and the one or more additional arbiters over a first predetermined period of time. The throttle circuit, responsive to a low activity state, limits a number of read and write commands issued by the arbiter during a second predetermined period of time.

公开(公告)号：US20240004801A1

公开(公告)日：2024-01-04

申请号：US17853340

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Shaizeen Dilawarhusen Aga ,  Vignesh Adhinarayanan

IPC: G06F12/14 ,  G06F9/30

CPC classification number: G06F12/1408 ,  G06F9/3004 ,  G06F9/30029

Abstract: An encryption circuit includes an iterative block cipher circuit. The iterative block cipher circuit has a counter input for a row index, a key input for receiving a secret key, and an output for providing an encrypted counter value in response to performing a block cipher process using the row index as a counter the secret key. The encryption circuit uses the iterative block cipher circuit during a row operation to a memory.

公开(公告)号：US20240004721A1

公开(公告)日：2024-01-04

申请号：US17853294

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5038 ,  G06F9/5033 ,  G06F9/5016

Abstract: An apparatus and method for efficiently performing power management for a multi-client computing system. In various implementations, a computing system includes multiple clients that process tasks corresponding to applications. The clients store generated requests of a particular type while processing tasks. A client receives an indication specifying that another client is having requests of the particular type being serviced. In response to receiving this indication, the client inserts a first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing. When the client determines a particular time interval has elapsed, the client sends an indication to other clients specifying that requests of the particular type are being serviced. The client also inserts a second urgency level different from the first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing.

公开(公告)号：US20240004657A1

公开(公告)日：2024-01-04

申请号：US17855621

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar Arunachalam ,  Manivannan Bhoopathy ,  Hon-Hin Wong ,  Scott Thomas Bingham

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3838

Abstract: The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240004656A1

公开(公告)日：2024-01-04

申请号：US17853790

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Elliott David Binder ,  Onur Kayiran ,  Masab Ahmad

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3851 ,  G06F9/3887

Abstract: Methods and systems are disclosed for processing a vector by a vector processor. Techniques disclosed include receiving predicated instructions by a scheduler, each of which is associated with an opcode, a vector of elements, and a predicate. The techniques further include executing the predicated instructions. Executing a predicated instruction includes compressing, based on an index derived from a predicate of the instruction, elements in a vector of the instruction, where the elements in the vector are contiguously mapped, then, after the mapped elements are processed, decompressing the processed mapped elements, where the processed mapped elements are reverse mapped based on the index.

公开(公告)号：US20240004448A1

公开(公告)日：2024-01-04

申请号：US17853759

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Eric D. Meyer ,  Austin Hung ,  Tianshu Liu

IPC: G06F1/28 ,  G06F11/30

CPC classification number: G06F1/28 ,  G06F11/3062

Abstract: Systems, apparatuses, and methods for dynamically estimating power losses in a computing system. A system management circuit tracks a state of a computing system and dynamically estimates power losses in the computing system based in part on the state. Based on the estimated power losses, power consumption of the computing system is estimated. In response to detecting reduced power losses in at least a portion of the computing system, the system management circuit is configured to increase a power-performance state of one or more circuits of the computing system while remaining within a power allocation limit of the computing system.