公开(公告)号：US20230385149A1

公开(公告)日：2023-11-30

申请号：US18313686

申请日：2023-05-08

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F11/10 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F12/0246 ,  G06F13/1668

Abstract: In accordance with an embodiment, a method includes: performing a first write operation comprising writing a first data packet to a first portion of a first line of a flash memory; and performing a second write operation comprising writing a second data packet to a second portion of the first line of the flash memory, wherein the first line comprises the first data packet and the second data packet after performing the first write operation and the second write operation.

公开(公告)号：US20230361528A1

公开(公告)日：2023-11-09

申请号：US18193190

申请日：2023-03-30

Applicant: STMicroelectronics (Alps) SAS

Inventor： Xavier Branca

IPC: H01S5/062 ,  H01S5/00 ,  H01S5/06 ,  G01S7/484 ,  G01S17/10

CPC classification number: H01S5/062 ,  H01S5/0014 ,  H01S5/0617 ,  G01S7/484 ,  G01S17/10

Abstract: In according with an embodiment, a method for power supplying a laser diode includes: generating a power supply current injected directly into the laser diode; generating a power supply voltage biasing terminals of the laser diode; measuring a temperature in a vicinity of the laser diode; and controlling the power supply current at an adjusted intensity according to the measured temperature or controlling the power supply voltage at an adjusted level according to the measured temperature.

公开(公告)号：US20230327469A1

公开(公告)日：2023-10-12

申请号：US18335690

申请日：2023-06-15

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Alexandre Pons ,  Jean Camiolo ,  Meriem Mersel

IPC: H02J7/00

CPC classification number: H02J7/00712 ,  H02J7/007192 ,  H02J2207/20 ,  H02J2207/30

Abstract: An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.

公开(公告)号：US20230318171A1

公开(公告)日：2023-10-05

申请号：US18194855

申请日：2023-04-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Olivier Ptak ,  Ouafa Hajji ,  Georg Kimmich

IPC: H01Q1/40 ,  H01Q1/48 ,  H01Q1/22 ,  H01Q9/04 ,  H05K3/10 ,  H05K3/28

CPC classification number: H01Q1/40 ,  H01Q1/48 ,  H01Q1/22 ,  H01Q9/0407 ,  H05K3/107 ,  H05K3/28

Abstract: An electronic device includes an electronic chip assembled on a first region of a substrate of the electronic device, a first coating layer of a first coating material covering a surface of the electronic chip facing away from the substrate, and a radiation element of an antenna of the electronic device separated from the substrate by at least a portion of the first coating layer and being offset with respect to the first region of the substrate so that the radiation element does not cover the electronic chip. The radiation element is buried in the first coating layer or is arranged in the first coating layer and partly covered with a protection material.

公开(公告)号：US20230297126A1

公开(公告)日：2023-09-21

申请号：US18119535

申请日：2023-03-09

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Alexandre TRAMONI ,  Florent SIBILLE ,  Patrick ARNOULD

IPC: G05F1/46 ,  H04B5/00

CPC classification number: G05F1/46 ,  H04B5/0037

Abstract: An electronic device includes a near-field communication module and a powering circuit for delivering a power supply voltage to the near-field communication module. When the near-field communication module is in a low power mode, the powering circuit is configured for an operational mode where it is periodically started to provide the power supply voltage.

公开(公告)号：US11757477B2

公开(公告)日：2023-09-12

申请号：US17187024

申请日：2021-02-26

Applicant: STMicroelectronics (Alps) SAS

Inventor： Frederic Rivoirard ,  Felix Gauthier

IPC: H04B1/00 ,  H03D7/12 ,  H04W88/06

CPC classification number: H04B1/0096 ,  H03D7/125 ,  H04W88/06

Abstract: An embodiment integrated electronic device comprises a mixer module including a voltage/current transconductor stage including first transistors and connected to a mixing stage including second transistors, wherein the mixing stage includes a resistive degeneration circuit connected to the sources of the second transistors and a calibration input connected to the gates of the second transistors and intended to receive an adjustable calibration voltage, and the sources of the first transistors are directly connected to a cold power supply point.

公开(公告)号：US11756874B2

公开(公告)日：2023-09-12

申请号：US17945822

申请日：2022-09-15

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Claire Laporte ,  Deborah Cogoni ,  Laurent Schwartz

IPC: H01L23/50 ,  H01L23/31

CPC classification number: H01L23/50 ,  H01L23/315 ,  H01L23/3128

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

公开(公告)号：US11700174B2

公开(公告)日：2023-07-11

申请号：US16951198

申请日：2020-11-18

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Nicolas Anquet ,  Loic Pallardy

IPC: H04L41/0803 ,  H04L41/0813 ,  H04L49/109 ,  G06F15/173 ,  G06F15/177 ,  G06F21/85

CPC classification number: H04L41/0813 ,  G06F15/177 ,  G06F15/17306 ,  H04L41/0803 ,  H04L49/109 ,  G06F21/85

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

公开(公告)号：US11698993B2

公开(公告)日：2023-07-11

申请号：US17161544

申请日：2021-01-28

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Gilles Pelissier ,  Nicolas Anquet ,  Delphine Le-Goascoz

IPC: G06F21/72 ,  H04L9/06 ,  H04L9/08

CPC classification number: G06F21/72 ,  H04L9/06 ,  H04L9/0866 ,  G06F2221/2113

Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.

公开(公告)号：US11663365B2

公开(公告)日：2023-05-30

申请号：US16928901

申请日：2020-07-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (ALPS) SAS

Inventor： Marc Benveniste ,  Fabien Journet ,  Fabrice Marinet

IPC: G06F21/44 ,  G06F21/72 ,  G06F21/75 ,  G06F1/08 ,  G06F3/12 ,  H04L9/32

CPC classification number: G06F21/75 ,  G06F1/08 ,  G06F3/1238 ,  G06F21/44 ,  G06F21/72 ,  H04L9/3236 ,  H04L9/3247

Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.