公开(公告)号：US20180269115A1

公开(公告)日：2018-09-20

申请号：US15897003

申请日：2018-02-14

Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Emmanuel Richard ,  Olivier Weber

IPC: H01L21/84 ,  H01L29/51 ,  H01L27/12 ,  H01L21/28

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/51

Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.

公开(公告)号：US20180255171A1

公开(公告)日：2018-09-06

申请号：US15799152

申请日：2017-10-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Demaj ,  Laurent Folliot

IPC: H04M1/725 ,  H04W4/02 ,  G01D21/02

Abstract: A method can be used for managing a real-time detection related to a scene. A succession of steps of scene detection is spaced apart by time intervals. A time interval separating a current step of scene detection from a previous step of scene detection is adjusted according to an adjustment criterion linked to a previous scene actually detected. The succession of steps and the adjustment are performed by a wireless communication apparatus.

公开(公告)号：US10049991B2

公开(公告)日：2018-08-14

申请号：US15596772

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/522 ,  H01L21/70 ,  H01L21/768 ,  H01L23/52 ,  H01L23/00 ,  H01L23/28 ,  H01L23/528 ,  H01L21/56

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.

公开(公告)号：US10049982B2

公开(公告)日：2018-08-14

申请号：US15596877

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.

公开(公告)号：US10049741B2

公开(公告)日：2018-08-14

申请号：US15436829

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  G11C16/14 ,  G11C16/12 ,  H01L29/423

Abstract: A memory cell includes a source region and a drain region disposed in a semiconductor body. A channel region is disposed in the semiconductor body between the source region and the drain region. A floating gate is disposed between the semiconductor body and the control gate. The floating gate includes a protruding portion that is located over the channel region between the source and drain regions and spaced therefrom. The protruding portion is separated from the channel region by a first insulating layer that is thinner than a second insulating layer that separates remaining portions of the floating gate from the channel region.

公开(公告)号：US10020580B2

公开(公告)日：2018-07-10

申请号：US14835103

申请日：2015-08-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Rizzo

IPC: H01Q7/00 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q1/50

CPC classification number: H01Q7/00 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q1/50 ,  H01Q1/528

Abstract: A radio or power transfer antenna, in the form of a planar conductive winding, with one of two ends of the planar conductive winding directly connected to a metal section or plane which continuously surrounds the planar conductive winding.

公开(公告)号：US20180189624A1

公开(公告)日：2018-07-05

申请号：US15798553

申请日：2017-10-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge ,  Jimmy Fort

IPC: G06K19/073 ,  H01L23/00 ,  G06F21/44

CPC classification number: G06K19/07363 ,  G06F21/445 ,  G06F21/75 ,  G06F21/755 ,  H01L23/576 ,  H01L2224/48228

Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

公开(公告)号：US20180189205A1

公开(公告)日：2018-07-05

申请号：US15701003

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Dragos Davidescu ,  Sandrine Lendre ,  Olivier Ferrand

IPC: G06F13/16 ,  G06F1/32 ,  G06F13/24

CPC classification number: G06F13/1673 ,  G06F1/3243 ,  G06F1/3293 ,  G06F13/24 ,  Y02D10/122 ,  Y02D10/152

Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.

公开(公告)号：US20180181968A1

公开(公告)日：2018-06-28

申请号：US15901003

申请日：2018-02-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Denis Farison ,  Fabrice Romain ,  Christophe Laurencin

IPC: G06Q30/00 ,  G06F21/44 ,  G06F21/73

CPC classification number: G06Q30/018 ,  G06F21/44 ,  G06F21/73

Abstract: In order to verify the authenticity of a product associated with a host device, the product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The host device sends a control signal for selecting and activating one of those ciphered functions. The product then deciphers and executes the function. The result of the function execution is then communicated back to host device when a decision on product authenticity is made.

公开(公告)号：US20180151231A1

公开(公告)日：2018-05-31

申请号：US15607636

申请日：2017-05-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesca Grande ,  Francesco La Rosa ,  Gianbattista Lo Giudice ,  Giovanni Matranga

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/26 ,  G11C16/3445

Abstract: A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.