公开(公告)号：US20240413230A1

公开(公告)日：2024-12-12

申请号：US18331305

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Mu-Chieh Chang ,  Shu Ling Liao ,  Zhen-Cheng Wu ,  Sung-En Lin ,  Tze-Liang Lee

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a substrate; a fin protruding above the substrate; a gate structure over the fin; source/drain regions over the fin and on opposing sides of the gate structure; channel layers over the fin and between the source/drain regions, where the gate structure wraps around the channel layers; and isolation structures under the source/drain regions, where the isolation structures separate the source/drain regions from the fin, where each of the isolation structures includes a liner layer and a dielectric layer over the liner layer, where the dielectric layer has a plurality of sublayers.

公开(公告)号：US20240413101A1

公开(公告)日：2024-12-12

申请号：US18452257

申请日：2023-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/58 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: In an embodiment, a package includes an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer, a first seal ring, and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds, and wherein the integrated circuit die overlaps the first seal ring. A sidewall of the integrated circuit die is exposed at an outer sidewall of the package.

公开(公告)号：US12166128B2

公开(公告)日：2024-12-10

申请号：US18360344

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US12166088B2

公开(公告)日：2024-12-10

申请号：US17854817

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting Fang ,  Chung-Hao Cai ,  Jui-Ping Lin ,  Chia-Hsien Yao ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

公开(公告)号：US12166074B2

公开(公告)日：2024-12-10

申请号：US17651869

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Hsiang-Pi Chang ,  Huang-Lin Chao ,  Chung-Liang Cheng ,  Chi On Chui ,  Kun-Yu Lee ,  Tzer-Min Shen ,  Yen-Tien Tung ,  Chun-I Wu

IPC: H01L21/00 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

公开(公告)号：US12166069B2

公开(公告)日：2024-12-10

申请号：US18351149

申请日：2023-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

Inventor： Zheng-Long Chen

IPC: H01L29/06 ,  H01L21/04 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L21/765 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/36 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H10B63/00

Abstract: A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.

公开(公告)号：US12165985B2

公开(公告)日：2024-12-10

申请号：US17818625

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Han-Ping Pu ,  Ting-Chu Ko

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

公开(公告)号：US12165936B2

公开(公告)日：2024-12-10

申请号：US17648836

申请日：2022-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui Fu Hsieh ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yi-Jen Chen ,  Chia-Cheng Tai

IPC: H01L21/66 ,  H01L21/311

Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.

公开(公告)号：US12165909B2

公开(公告)日：2024-12-10

申请号：US17871826

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Ru Chen ,  Yan-Hong Liu ,  Che-Fu Chen

IPC: H01L21/687 ,  C23C16/458 ,  H01J37/32 ,  H01L21/683 ,  C23C16/455 ,  H01L21/768

Abstract: In an embodiment, a system includes: a gas distributor assembly configured to dispense gas into a chamber; and a chuck assembly configured to secure a wafer within the chamber, wherein at least one of the gas distributor assembly and the chuck assembly includes: a first portion comprising a convex protrusion, and a second portion comprising a concave opening, wherein the convex protrusion is configured to engage the concave opening.

公开(公告)号：US12164211B2

公开(公告)日：2024-12-10

申请号：US18128737

申请日：2023-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lan-Chou Cho ,  Chewn-Pu Jou ,  Min-Hsiang Hsu

IPC: G02F1/225 ,  G02F1/21

Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.