公开(公告)号：US11379392B2

公开(公告)日：2022-07-05

申请号：US16942380

申请日：2020-07-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US11323118B1

公开(公告)日：2022-05-03

申请号：US17007232

申请日：2020-08-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03K19/0944 ,  H03K19/20

Abstract: A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.

公开(公告)号：US11307243B2

公开(公告)日：2022-04-19

申请号：US16924321

申请日：2020-07-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G01R31/28 ,  G01R31/317 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C29/50 ,  G01R31/26 ,  H03L7/00 ,  G11C29/04

Abstract: A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

公开(公告)号：US11301378B2

公开(公告)日：2022-04-12

申请号：US16652234

申请日：2018-10-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US20220101912A1

公开(公告)日：2022-03-31

申请号：US17501311

申请日：2021-10-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20220101908A1

公开(公告)日：2022-03-31

申请号：US17391521

申请日：2021-08-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C11/4076 ,  G11C7/22 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18 ,  G11C7/10 ,  G06F1/10 ,  G11C11/409

Abstract: An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.

公开(公告)号：US11264085B1

公开(公告)日：2022-03-01

申请号：US16927892

申请日：2020-07-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G06F12/14 ,  G11C11/408 ,  G11C11/4072 ,  G11C29/38 ,  G11C29/32 ,  G11C29/22 ,  G11C7/10 ,  G11C5/04

Abstract: In a memory component having a page buffer with 2N independently accessible regions, N bits of a command/address value are decoded to access contents within a first one of the 2N page-buffer regions if a configuration value specifies a first addressing resolution and, if the configuration value specifies a second addressing resolution, a composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated within the memory component to access contents within a second one of the 2N page-buffer regions.

公开(公告)号：US11249649B2

公开(公告)日：2022-02-15

申请号：US16805535

申请日：2020-02-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G06F12/06

Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

公开(公告)号：US11195570B2

公开(公告)日：2021-12-07

申请号：US16549992

申请日：2019-08-23

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Frederick A. Ware

IPC: G06F13/42 ,  G11C11/4076 ,  G06F1/04 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04 ,  G11C29/02 ,  H04L7/00

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US11194749B2

公开(公告)日：2021-12-07

申请号：US16365535

申请日：2019-03-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kishore Kasamsetty

IPC: G06F13/40 ,  G06F12/02 ,  G06F13/16 ,  G06F12/00 ,  G06F3/06 ,  G06F13/42 ,  G11C5/02

Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.