公开(公告)号：US20200081641A1

公开(公告)日：2020-03-12

申请号：US16686200

申请日：2019-11-17

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G11C11/56 ,  G06F12/02

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US20200042244A1

公开(公告)日：2020-02-06

申请号：US16296161

申请日：2019-03-07

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06 ,  G06F11/10

Abstract: A method for performing storage control in a storage server may include: regarding any memory device of a plurality of memory devices installed at the storage server, assigning a channel of multiple channels within the memory device for access control corresponding to a thread of a plurality of threads running on the storage server, wherein the storage server configures the plurality of memory devices to form a RAID of the storage server; and during storing a series of logical access units (LAUs) into the RAID, writing information into respective sets of pages of the plurality of memory devices as pages in a LAU of the series of LAUs according to a predetermined arrangement rule, to make the respective sets of pages be sequentially written into the plurality of memory devices respectively with aid of the assignment of the channel of the multiple channels to the thread. Associated apparatus are provided.

公开(公告)号：US10552262B2

公开(公告)日：2020-02-04

申请号：US15948586

申请日：2018-04-09

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F3/06 ,  G11C29/04

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

公开(公告)号：US20200026475A1

公开(公告)日：2020-01-23

申请号：US16429057

申请日：2019-06-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/26

Abstract: The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.

公开(公告)号：US20200026470A1

公开(公告)日：2020-01-23

申请号：US16505701

申请日：2019-07-08

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method includes the steps of: sending a read command to the flash memory module to ask for data on at least one memory unit; receiving multi-bit information of a plurality of memory cells of the at least one memory unit from the flash memory module; and analyzing the multi-bit information of the plurality of memory cells to obtain a threshold voltage distribution of the plurality of memory cells for determining a decoding process.

公开(公告)号：US10469105B2

公开(公告)日：2019-11-05

申请号：US15260330

申请日：2016-09-09

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Sheng-I Hsu

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/02 ,  H03M13/09 ,  H03M13/29 ,  H03M13/13

Abstract: A data storage system includes: a processing circuit arranged to receive a data bytes from a host; a calculating circuit arranged to generate a cyclic redundancy check code according to a logical block address, and combine the cyclic redundancy check code and the data bytes to be a data sector; and an encoding circuit arranged to encode the data sector to generate an error checking and correcting code, and combine the data sector and the error checking and correcting code to be a storing data.

公开(公告)号：US20190220353A1

公开(公告)日：2019-07-18

申请号：US16361200

申请日：2019-03-21

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/08 ,  G11C11/56 ,  G06F3/06 ,  G11C16/16 ,  G11C16/26

CPC classification number: G06F11/1072 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0688 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

公开(公告)号：US20190122738A1

公开(公告)日：2019-04-25

申请号：US16228007

申请日：2018-12-20

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/3431

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

公开(公告)号：US20190073263A1

公开(公告)日：2019-03-07

申请号：US16184925

申请日：2018-11-08

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu ,  Jian-Dong Du

IPC: G06F11/10 ,  G11C11/56 ,  G11C29/52 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

公开(公告)号：US20190036549A1

公开(公告)日：2019-01-31

申请号：US16132461

申请日：2018-09-16

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: H03M13/29 ,  G06F11/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04 ,  G06F12/0802 ,  G06F12/02 ,  G06F11/14 ,  G11C7/10 ,  H03M13/11 ,  G11C29/52

CPC classification number: H03M13/29 ,  G06F11/10 ,  G06F11/1072 ,  G06F11/1402 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7207 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C29/52 ,  G11C2211/5641 ,  H03M13/1102

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.