公开(公告)号：US11450741B2

公开(公告)日：2022-09-20

申请号：US17201041

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US11450565B2

公开(公告)日：2022-09-20

申请号：US16997616

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Cheng Chen ,  Huicheng Chang ,  Fu-Ming Huang ,  Kei-Wei Chen ,  Liang-Yin Chen ,  Tang-Kuei Chang ,  Yee-Chia Yeo ,  Wei-Wei Liang ,  Ji Cui

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535 ,  H01L23/532

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US20220230911A1

公开(公告)日：2022-07-21

申请号：US17150552

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Meng-Han Chou

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

公开(公告)号：US20220230908A1

公开(公告)日：2022-07-21

申请号：US17150490

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Kai Hsiao ,  Han-De Chen ,  Tsai-Yu Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/28

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region forms a semiconductor fin.

公开(公告)号：US11348792B2

公开(公告)日：2022-05-31

申请号：US17181665

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Jie Liu ,  Chun-Feng Nieh ,  Huicheng Chang

IPC: H01L21/265 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/266 ,  H01L27/11 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the deep-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.

公开(公告)号：US11289417B2

公开(公告)日：2022-03-29

申请号：US16805834

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Liang-Yin Chen ,  Su-Hao Liu ,  Tze-Liang Lee ,  Meng-Han Chou ,  Kuo-Ju Chen ,  Huicheng Chang ,  Tsai-Jung Ho ,  Tzu-Yang Ho

IPC: H01L23/522 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

公开(公告)号：US20220028707A1

公开(公告)日：2022-01-27

申请号：US16934762

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  H01L21/265

Abstract: Embodiments of an ion cryo-implantation process utilize a post implantation heating stage to heat the implanted wafer while under the heavy vacuum used during cryo-implantation. The implanted wafer is then transferred to load locks which are held at a lesser vacuum than the heavy vacuum.

公开(公告)号：US20210327749A1

公开(公告)日：2021-10-21

申请号：US16939718

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yen Chen ,  Li-Ting Wang ,  Wan-Chen Hsieh ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/02 ,  H01L21/768

Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

公开(公告)号：US11133415B2

公开(公告)日：2021-09-28

申请号：US17007825

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Hao Lin ,  Chun-Feng Nieh ,  Yu-Chang Lin ,  Huicheng Chang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L21/265 ,  H01L29/165 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/11 ,  H01L21/306

Abstract: An embodiment is a method of manufacturing a semiconductor device. The method includes forming a fin on a substrate. A gate structure is formed over the fin. A recess is formed in the fin proximate the gate structure. A gradient doped region is formed in the fin with a p-type dopant. The gradient doped region extends from a bottom surface of the recess to a vertical depth below the recess in the fin. A source/drain region is formed in the recess and on the gradient doped regions.

公开(公告)号：US20210257255A1

公开(公告)日：2021-08-19

申请号：US17227831

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Wen-Yen Chen ,  Tz-Shian Chen ,  Cheng-Jung Sung ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.