公开(公告)号：US07611949B2

公开(公告)日：2009-11-03

申请号：US11309205

申请日：2006-07-13

Applicant: San-Jung Chang ,  Jim Lin

Inventor： San-Jung Chang ,  Jim Lin

IPC: H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L29/42368 ,  H01L29/66553 ,  H01L29/66621

Abstract: A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the sidewall of the patterned hard mask layer in the opening. An isotropic etching process is performed on the substrate to form a recess in the substrate. An ion implant process is performed on the substrate in the lower portion of the recess using oxidation-restrained ions. The spacer is removed. Then, a thermal process is performed to form a gate oxide layer on the surface of the substrate within the recess such that the gate oxide layer in the upper portion of the recess is thicker than that in the lower portion of the recess.

Abstract translation: 提供一种制造金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成具有开口的图案化的硬掩模层。 在开口中的图案化硬掩模层的侧壁上形成间隔物。 在基板上进行各向同性蚀刻处理，以在基板中形成凹部。 使用氧化抑制离子在凹部的下部的基板上进行离子注入工艺。 移除间隔物。 然后，进行热处理，以在凹部内的基板的表面上形成栅极氧化层，使得凹部的上部的栅极氧化物层比凹部的下部的栅极氧化物层厚。

公开(公告)号：US20090239315A1

公开(公告)日：2009-09-24

申请号：US12111973

申请日：2008-04-30

Applicant: Yung-Yao Lee

Inventor： Yung-Yao Lee

IPC: H01L21/66 ,  G06F17/50 ,  G01R31/00

CPC classification number: G03F7/70425 ,  G03F7/70533 ,  G03F7/70625 ,  G03F7/70633

Abstract: A method and a system for processing a test wafer in a photolithography process are provided for processing an ith layer of the test wafer, and i is a positive integer. In the present method, a compensation value is calculated according to historical compensation behaviors of an equipment, relationships between the ith layer and other layers, and offsets generated in performing a non-photolithography process on the test wafer. Then, the test wafer is processed according to the compensation value. A determination on whether the test wafer meets a design specification is then made. Rework is performed on the test wafer if the test wafer does not meet the design specification. Accordingly, an adjustable compensation value is used to process the test wafer and avoid unnecessary rework. The possibility of rework on the test wafer is reduced so as to increase the efficiency of the photolithography process.

Abstract translation: 提供了一种在光刻工艺中处理测试晶片的方法和系统，用于处理测试晶片的第i层，i为正整数。 在本方法中，根据设备的历史补偿行为，第i层与其他层之间的关系以及在测试晶片上执行非光刻工艺产生的偏移来计算补偿值。 然后，根据补偿值对测试晶片进行处理。 然后确定测试晶片是否符合设计规范。 如果测试晶片不符合设计规范，则在测试晶片上进行返工。 因此，使用可调整的补偿值来处理测试晶片并避免不必要的返工。 降低了在测试晶片上返工的可能性，从而提高了光刻工艺的效率。

公开(公告)号：US20090146127A1

公开(公告)日：2009-06-11

申请号：US12135041

申请日：2008-06-06

Applicant: Ming-Jeng Huang ,  Yung-Fa Lin

Inventor： Ming-Jeng Huang ,  Yung-Fa Lin

IPC: H01L47/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: Phase change memories comprising a top electrode, a phase change element, a plurality of via holes allocated between the top electrode and the phase change element, at least four heaters aiming at different regions of the phase change element, and a plurality of bottom electrodes and transistors corresponding to the heaters. The bottom electrodes are respectively coupled to the heaters. Regarding the transistors, their first terminals are respectively coupled to the bottom electrodes, their control terminals are used for coupling to word lines, and their second terminals are used for coupling to bit lines. In an embodiment with four heaters, the regions the heaters aimed at the phase change element form a 2×2 storage array.

Abstract translation: 相变存储器，包括顶电极，相变元件，分配在顶电极和相变元件之间的多个通孔，至少四个对准相变元件的不同区域的加热器，以及多个底电极和 对应于加热器的晶体管。 底部电极分别连接到加热器。 关于晶体管，它们的第一端子分别耦合到底部电极，它们的控制端子用于耦合到字线，并且它们的第二端子用于耦合到位线。 在具有四个加热器的实施例中，加热器瞄准相变元件的区域形成2x2存储阵列。

公开(公告)号：US20090039295A1

公开(公告)日：2009-02-12

申请号：US12033892

申请日：2008-02-20

Applicant: Hung-Pin Yu ,  Hsueh-Li Chiang ,  Cheng-Da Wu ,  Shiu-Shien Hsheng

Inventor： Hung-Pin Yu ,  Hsueh-Li Chiang ,  Cheng-Da Wu ,  Shiu-Shien Hsheng

IPC: G21F3/00

CPC classification number: H01J37/3171 ,  H01J37/32623 ,  H01J2237/0206 ,  H01J2237/022 ,  H01J2237/026 ,  H01J2237/038 ,  H01J2237/08 ,  H01J2237/16

Abstract: A detachable inner shield suitable for an isolation bushing of an ion implanter is provided. The inner shield is mounted on an inside of the isolation bushing and completely fitting the inside of the isolation bushing.

Abstract translation: 提供了一种适用于离子注入机隔离套管的可拆卸内屏蔽罩。 内屏蔽安装在隔离套管的内侧，并完全安装在隔离套管的内部。

公开(公告)号：US20090032794A1

公开(公告)日：2009-02-05

申请号：US11965569

申请日：2007-12-27

Applicant: Tsai-Chu Hsiao

Inventor： Tsai-Chu Hsiao

IPC: H01L29/06 ,  H01L21/425

CPC classification number: H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126

Abstract: A phase change memory device is disclosed. A first dielectric layer having a sidewall is provided. A bottom electrode is adjacent to the sidewall of the first dielectric layer, wherein the bottom electrode comprises a seed layer and a conductive layer. A second dielectric layer is adjacent to a side of the bottom electrode opposite the sidewall of the first dielectric layer. A top electrode couples the bottom electrode through a phase change layer.

Abstract translation: 公开了一种相变存储器件。 提供具有侧壁的第一电介质层。 底部电极与第一电介质层的侧壁相邻，其中底部电极包括种子层和导电层。 第二电介质层邻近与第一电介质层的侧壁相对的底部电极的一侧。 顶部电极通过相变层将底部电极耦合。

公开(公告)号：US20090017597A1

公开(公告)日：2009-01-15

申请号：US11969726

申请日：2008-01-04

Applicant: PETER HAI JUN ZHAO ,  YU CHI CHEN ,  YU SHENG LIU

Inventor： PETER HAI JUN ZHAO ,  YU CHI CHEN ,  YU SHENG LIU

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3115 ,  H01L21/76229 ,  H01L21/76237

Abstract: A method for manufacturing semiconductor shallow trench isolation is performed as follows. First, a semiconductor substrate including at least one shallow trench is provided, and the shallow trench is filled with Spin-On-Dielectric (SOD) material, e.g., polysilazane, to form a SOD material layer. Then, the SOD material layer is subjected to a planarization process. Oxygen ions are implanted into the SOD material layer to a predetermined depth, and a high temperature process is performed afterwards to transform the portion of the SOD material layer having oxygen ions into a silicon oxide layer. The oxygen ions can be implanted by plasma doping, immersion doping or ion implantation.

Abstract translation: 半导体浅沟槽隔离的制造方法如下进行。 首先，提供包括至少一个浅沟槽的半导体衬底，并且用诸如聚硅氮烷之类的旋转电介质（SOD）材料填充浅沟槽，以形成SOD材料层。 然后，对SOD材料层进行平坦化处理。 将氧离子注入SOD材料层至预定深度，然后进行高温处理，以将具有氧离子的SOD材料层的部分转化为氧化硅层。 可以通过等离子体掺杂，浸渍掺杂或离子注入来注入氧离子。

公开(公告)号：US20080286936A1

公开(公告)日：2008-11-20

申请号：US11774934

申请日：2007-07-09

Applicant: Hai Jun Zhao

Inventor： Hai Jun Zhao

IPC: H01L21/76

CPC classification number: H01L21/76235 ,  H01L21/76237

Abstract: A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench.

Abstract translation: 一种用于制备浅沟槽隔离的方法，包括以下步骤：在半导体衬底中形成至少一个沟槽，执行植入工艺以将含氮掺杂剂注入到沟槽的上侧壁中，使得含氮掺杂剂的浓度在 上侧壁高于沟槽的底侧壁中的上侧壁，形成填充沟槽并覆盖半导体衬底的表面的旋涂电介质层，进行热氧化工艺以形成覆盖内侧壁的氧化硅层。 由于含氮掺杂剂可以抑制氧化速度，并且上部内侧壁中的含氮掺杂剂的浓度高于沟槽的底部内侧壁中的含氮掺杂剂的浓度，所以通过热氧化形成的氧化硅层的厚度 处理在底部比在沟槽的上部处更大。

公开(公告)号：US20080283812A1

公开(公告)日：2008-11-20

申请号：US11961452

申请日：2007-12-20

Applicant: Michael Y. Liu

Inventor： Michael Y. Liu

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

Abstract: A phase-change memory element. The phase-change memory comprises first and second electrodes. A phase-change material layer is formed between the first and second electrodes. And a carbon-doped oxide dielectric layer is formed to surround the phase-change material layer, wherein the first electrode electrically connects the second electrodes via the phase-change material layer.

Abstract translation: 相变存储元件。 相变存储器包括第一和第二电极。 在第一和第二电极之间形成相变材料层。 并且形成碳掺杂氧化物电介质层以包围所述相变材料层，其中所述第一电极经由所述相变材料层电连接所述第二电极。

公开(公告)号：US20080275578A1

公开(公告)日：2008-11-06

申请号：US12175865

申请日：2008-07-18

Applicant: HONG MING CHANG ,  JUI WEN HU ,  HUNG WEN CHIOU

Inventor： HONG MING CHANG ,  JUI WEN HU ,  HUNG WEN CHIOU

IPC: G05B9/02

CPC classification number: G05B19/4183 ,  G05B2219/31244 ,  Y02P90/10 ,  Y02P90/14

Abstract: A data collector control system for semiconductor manufacturing comprises a data collector and a automatic communication port switch control circuit. The control system is placed between an equipment and an equipment automation programming (EAP) system. The data collector processes and transmits communication messages between the equipment and the EAP system while the data collector operates normally. The communication messages between the equipment and the EAP system are transmitted through the control circuit instead of the data collector while the data collector operates abnormally.

Abstract translation: 用于半导体制造的数据采集器控制系统包括数据采集器和自动通信端口开关控制电路。 控制系统位于设备和设备自动化程序设计（EAP）系统之间。 数据采集​​器在数据采集器正常工作的同时处理和传输设备与EAP系统之间的通信消息。 设备和EAP系统之间的通信信息通过控制电路而不是数据采集器传输，而数据采集器工作异常。

公开(公告)号：US20080265238A1

公开(公告)日：2008-10-30

申请号：US12056227

申请日：2008-03-26

Applicant: Frederick T. Chen ,  Yen Chuo ,  Hong-Hui Hsu ,  Jyi-Tyan Yeh ,  Ming-Jinn Tsai

Inventor： Frederick T. Chen ,  Yen Chuo ,  Hong-Hui Hsu ,  Jyi-Tyan Yeh ,  Ming-Jinn Tsai

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1691

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a first electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer and the first electrode. A phase change material layer disposed in the second dielectric layer to electrically contact the first electrode. A third dielectric layer is disposed over the second dielectric layer. A second electrode is disposed in the third dielectric layer to electrically connect the phase change material layer and at least one gap disposed in the first dielectric layer or the second dielectric layer to thereby isolate portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括设置在第一介电层中的第一电极。 第二电介质层设置在第一电介质层和第一电极之上。 一种相变材料层，设置在第二电介质层中以与第一电极电接触。 第三电介质层设置在第二电介质层上。 第二电极设置在第三电介质层中以将相变材料层和布置在第一介电层或第二介电层中的至少一个间隙电连接，从而隔离相变材料层的部分和第一或 第二电介质层。