公开(公告)号：US20230361207A1

公开(公告)日：2023-11-09

申请号：US18223543

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US11812667B2

公开(公告)日：2023-11-07

申请号：US17341316

申请日：2021-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.

公开(公告)号：US20230352587A1

公开(公告)日：2023-11-02

申请号：US18218098

申请日：2023-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/6656 ,  H01L29/6653 ,  H01L29/42364

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

公开(公告)号：US20230352557A1

公开(公告)日：2023-11-02

申请号：US17833885

申请日：2022-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L29/66 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/423 ,  H01L29/778 ,  H01L21/265 ,  H01L29/40

CPC classification number: H01L29/66462 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/42316 ,  H01L29/7786 ,  H01L21/26546 ,  H01L29/401

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A passivation layer is formed on the III-V compound barrier layer. A silicon layer is formed on the passivation layer, the III-V compound barrier layer, and the III-V compound semiconductor layer. A silicon implantation process is performed to the III-V compound semiconductor layer for forming a source doped region and a drain doped region in the III-V compound semiconductor layer under the silicon layer. A source electrode and a drain electrode are formed on the silicon layer. A source silicide layer is formed between the source electrode and the source doped region, and a drain silicide layer is formed between the drain electrode and the drain doped region. The source silicide layer and the drain silicide layer are partly formed on the passivation layer.

公开(公告)号：US20230350381A1

公开(公告)日：2023-11-02

申请号：US17749176

申请日：2022-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Ting Pan ,  Chung-Yi Chiu

IPC: G05B19/4099 ,  G06T7/13 ,  G06T7/73 ,  G03F7/20

CPC classification number: G05B19/4099 ,  G06T7/13 ,  G06T7/73 ,  G03F7/705 ,  G06T2207/10061 ,  G06T2207/30148 ,  G05B2219/35134

Abstract: A method of simulating a 3D feature profile by using a scanning electron microscope (SEM) image includes providing an SEM image. The SEM image includes a feature pattern within a material layer. The feature pattern includes an inner edge and an outer edge. The outer edge surrounds the inner edge. Then, the positions of the inner edge and the outer edge of the feature pattern are identified. Latter, a side edge region is defined based on the positions of the inner edge and the outer edge. Subsequently, a side edge model is generated automatically to simulate a profile of the feature pattern in the side edge region. Finally, a 3D feature profile is automatically output based on the position of the inner edge, the position of the outer edge, the thickness of the material layer and the side edge profile.

公开(公告)号：US20230350286A1

公开(公告)日：2023-11-02

申请号：US17749114

申请日：2022-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chieh Lai ,  Chih-Hsien Tang

IPC: G03F7/00 ,  B29C59/02

CPC classification number: G03F7/0002 ,  B29C59/022 ,  B29C59/026

Abstract: A method of forming patterns on a substrate by double nanoimprint processes includes providing a first replicate mold and a second replicate mold. The first replicate mold includes numerous first patterns. The second replicate mold includes at least one second pattern. The second pattern corresponds to at least one of the first patterns. Later, a first substrate is provided. A first polymeric compound layer is coated on the first substrate. Next, the first patterns are nanoimprinted into the first polymeric compound layer. Subsequently, the first substrate is etched by taking the first polymeric compound layer as a mask. After that, a second polymeric compound layer is coated on the first substrate. Later, the second pattern is nanoimprinted into the second polymeric compound layer. Finally, the first substrate is etched by taking the second polymeric compound layer as a mask.

公开(公告)号：US11804550B2

公开(公告)日：2023-10-31

申请号：US17705376

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78603 ,  H01L21/2253 ,  H01L21/762 ,  H01L21/8232 ,  H01L29/0653 ,  H01L29/66772 ,  H01L29/749

Abstract: A method for fabricating a field-effect transistor includes the following steps. A gate structure layer in a line shape including a first region and a second region abutting to the first region is formed on a silicon layer. A first implanting process is performed to implant first-type dopants at least into a second portion of the second region of the gate structure layer. A second implanting region is performed to implant second-type dopants into the silicon layer to form a source region and a second region corresponding to the first region of the gate structure layer. The gate structure layer has a conductive-type junction at an interface between the first and second portions of the second region. A width of the silicon layer under the second region of the gate structure layer is smaller than a width of the gate structure layer.

公开(公告)号：US11804544B2

公开(公告)日：2023-10-31

申请号：US17575655

申请日：2022-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/265 ,  H01L29/205 ,  H01L29/20 ,  H01L29/207 ,  H01L29/423 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/7786 ,  H01L21/26546 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66462 ,  H01L21/2654 ,  H01L21/28264 ,  H01L29/41766 ,  H01L29/4236

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US11800702B2

公开(公告)日：2023-10-24

申请号：US17202359

申请日：2021-03-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H10B12/00 ,  H01L21/308 ,  H01L21/762

CPC classification number: H10B12/482 ,  H01L21/3086 ,  H01L21/76224 ,  H10B12/053 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.

公开(公告)号：US11799031B2

公开(公告)日：2023-10-24

申请号：US17705380

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L21/8232 ,  H01L21/762 ,  H01L29/749 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225

CPC classification number: H01L29/78603 ,  H01L21/2253 ,  H01L21/762 ,  H01L21/8232 ,  H01L29/0653 ,  H01L29/66772 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.