公开(公告)号：US20090321711A1

公开(公告)日：2009-12-31

申请号：US12375881

申请日：2007-09-21

Applicant: Takeshi Takagi ,  Takumi Mikawa

Inventor： Takeshi Takagi ,  Takumi Mikawa

IPC: H01L47/00 ,  H01L21/16

CPC classification number: H01L45/04 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683

Abstract: A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12). A first area (22) where insulating layer or semiconductor layer (15) of the diode (18) is in contact with a first electrode (16) of the diode (18) is larger than at least one of a second area (23) where the resistance variable layer (11) is in contact with the upper electrode (13) and a third area (24) where the resistance variable layer (11) is in contact with the lower electrode (12).

Abstract translation: 本发明的非易失性存储元件（20）包括形成在基板（10）上的电阻可变元件（14）和二极管（18），使得电阻可变元件（14）具有电阻变化层（11 ）和位于下电极（12）和上电极（13）之间的二极管（18），以及与电阻可变元件（14）在层叠方向上串联连接并具有绝缘层或半导体层（15）的二极管 ）夹在下侧的第一电极（16）和上侧的第二电极（17）之间。 电阻变化层（11）嵌入形成在下电极（12）上的第一接触孔（21）中。 二极管（18）的绝缘层或半导体层（15）与二极管（18）的第一电极（16）接触的第一区域（22）大于第二区域（23）中的至少一个， 其中电阻变化层（11）与上电极（13）接触，电阻变化层（11）与下电极（12）接触的第三区域（24）。

公开(公告)号：US20090224224A1

公开(公告)日：2009-09-10

申请号：US12307032

申请日：2007-10-24

Applicant: Satoru Fujii ,  Takeshi Takagi ,  Shunsaku Muraoka ,  Koichi Osano ,  Kazuhiko Shimakawa

Inventor： Satoru Fujii ,  Takeshi Takagi ,  Shunsaku Muraoka ,  Koichi Osano ,  Kazuhiko Shimakawa

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (104), a resistance value of the resistance variable layer varying reversibly according to an electric signal applied between the electrodes (103),(105), and the resistance variable layer (104) comprises at least a tantalum oxide, and is configured to satisfy 0

Abstract translation: 本发明的非易失性存储元件包括第一电极（103），第二电极（105）和设置在第一电极（103）和第二电极（104）之间的电阻变化层（104），电阻值 根据施加在电极（103），（105）和电阻变化层（104）之间的电信号可逆地改变的电阻变化层至少包括氧化钽，并且被配置为满足0

公开(公告)号：US07473967B2

公开(公告)日：2009-01-06

申请号：US10558671

申请日：2004-05-31

Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC: H01L27/088

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

Abstract translation: 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由连接部的长度方向的至少一部分形成的通道区域（15a）; 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US07369232B2

公开(公告)日：2008-05-06

申请号：US11139777

申请日：2005-05-31

Applicant: Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

Inventor： Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

IPC: G01J4/00

CPC classification number: G01J4/00

Abstract: An object is to accurately measure the Stokes parameters, without the occurrence of polarization fluctuations or PDL during the splitting of the incident light. When the incident light is made incident on a first-stage prism, the light is split into two first splitting light rays. Next, the first split light rays are respectively incident on a pair of prisms of a second stage. Each of the pair of first split light rays is split into two rays by a second-stage prism, to obtain four second split light rays.

Abstract translation: 目的是精确测量斯托克斯参数，而不会在入射光分裂期间出现极化波动或PDL。 当入射光入射在第一级棱镜上时，光被分成两个第一分裂光线。 接下来，第一分裂光线分别入射到第二级的一对棱镜上。 一对第一分裂光线中的每一个被第二级棱镜分成两束，以获得四条第二分裂光线。

公开(公告)号：US20070108514A1

公开(公告)日：2007-05-17

申请号：US10554860

申请日：2004-04-28

Applicant: Akira Inoue ,  Takeshi Takagi ,  Haruyuki Sorada

Inventor： Akira Inoue ,  Takeshi Takagi ,  Haruyuki Sorada

IPC: H01L29/94

CPC classification number: H01L29/7834 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/78621

Abstract: A semiconductor device according to the present invention, which comprises a MISFET, has a semiconductor layer (3) having a recessed portion (101) formed in the surface thereof, the recessed portion (101) having an opening the outer circumference of which is closed, a gate insulating film (13) formed so as to cover at least the inner face of the recessed portion (3), a gate electrode (14) filling the recessed portion (101) such that the gate insulating film (13) is interposed between the gate electrode (14) and the inner face of the recessed portion (101), and a pair of source/drains (102), located on both sides of the gate electrode (14) when viewed in plan and formed to a predetermined depth from the surface of the semiconductor layer (3).

Abstract translation: 根据本发明的包括MISFET的半导体器件具有在其表面形成有凹部（101）的半导体层（3），所述凹部（101）的外周封闭的开口部 形成为至少覆盖所述凹部（3）的内面的栅极绝缘膜（13），填充所述凹部（101）的栅极电极（14），使得所述栅极绝缘膜（13）插入 在栅极电极（14）和凹部（101）的内表面之间，以及一对源极/漏极（102），位于栅极电极（14）的两侧，当从平面观察时形成预定的 从半导体层（3）的表面的深度。

公开(公告)号：US07119417B2

公开(公告)日：2006-10-10

申请号：US10948747

申请日：2004-09-24

Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC: H01L31/117

CPC classification number: H01L29/66636 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

Abstract translation: 本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于 通道层。

公开(公告)号：US07087473B2

公开(公告)日：2006-08-08

申请号：US10866093

申请日：2004-06-14

Applicant: Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

Inventor： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC: H01L29/80

CPC classification number: H01L21/823807

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

Abstract translation: 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US20060086988A1

公开(公告)日：2006-04-27

申请号：US11294566

申请日：2005-12-06

Applicant: Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

Inventor： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC: H01L21/8238 ,  H01L29/94

CPC classification number: H01L21/823807

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

Abstract translation: 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US06917075B2

公开(公告)日：2005-07-12

申请号：US10752409

申请日：2004-01-07

Applicant: Akira Inoue ,  Akira Asai ,  Teruhito Ohnishi ,  Haruyuki Sorada ,  Yoshihiro Hara ,  Takeshi Takagi

Inventor： Akira Inoue ,  Akira Asai ,  Teruhito Ohnishi ,  Haruyuki Sorada ,  Yoshihiro Hara ,  Takeshi Takagi

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66772 ,  H01L21/76895 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78621

Abstract: A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.

Abstract translation: 根据本发明的半导体器件及其制造方法是：在半导体衬底的预定区域上形成栅极绝缘体; 栅电极形成在栅极绝缘体上; 源极和漏极区域分别形成在预定区域的位于栅极电极的两侧的部分中; 由不同于所述源极和漏极区域的所述预定区域的区域形成的体区; 以及使所述栅电极和所述体区域电连接的触点，其中，与所述栅电极连接的所述触点的一部分在平面图中形成为与所述栅电极相交。

公开(公告)号：US20050087764A1

公开(公告)日：2005-04-28

申请号：US10978513

申请日：2004-11-02

Applicant: Akira Inoue ,  Takeshi Takagi ,  Akira Asai ,  Haruyuki Sorada

Inventor： Akira Inoue ,  Takeshi Takagi ,  Akira Asai ,  Haruyuki Sorada

IPC: H01J29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L31/0336

CPC classification number: H01L21/28123 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/66651 ,  H01L29/783

Abstract: A MISFET according to this invention includes: a substrate having a semiconductor layer; an active region formed in the semiconductor layer; a gate insulator formed on the active region; a gate formed on the gate insulator; and a source region and a drain region, wherein: the active region is formed, in plan view, to have a body portion and a projecting portion projecting from a periphery of the body portion; the gate is formed, in plan view, to intersect the body portion of the active region, cover a pair of connecting portions connecting a periphery of the projecting portion to the periphery of the body portion and allow a part of the projecting portion to project from a periphery of the gate; and the source region and the drain region are formed in regions of the body portion of the active region which are situated on opposite sides of the gate in plan view, respectively.

Abstract translation: 根据本发明的MISFET包括：具有半导体层的衬底; 形成在半导体层中的有源区; 形成在有源区上的栅极绝缘体; 形成在栅极绝缘体上的栅极; 源极区域和漏极区域，其中：有源区域在平面图中形成为具有从主体部分的周边突出的主体部分和突出部分; 在平面图中，门形成为与有源区域的主体部分相交，覆盖将突出部分的周边连接到主体部分的周边的一对连接部分，并使突出部分的一部分从 门的周边; 并且源极区域和漏极区域分别形成在有源区域的主体部分的位于平面图的栅极的相对侧上的区域中。