公开(公告)号：US20110147708A1

公开(公告)日：2011-06-23

申请号：US12643848

申请日：2009-12-21

Applicant: Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

Inventor： Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7783 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7785 ,  H01L29/7848 ,  H01L29/802 ,  H01L29/803

Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20110140171A1

公开(公告)日：2011-06-16

申请号：US13032777

申请日：2011-02-23

Applicant: Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L29/06

CPC classification number: H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20110121266A1

公开(公告)日：2011-05-26

申请号：US13017862

申请日：2011-01-31

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/06 ,  H01L21/20

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US20110062520A1

公开(公告)日：2011-03-17

申请号：US12949696

申请日：2010-11-18

Applicant: Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract translation: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。

公开(公告)号：US07884354B2

公开(公告)日：2011-02-08

申请号：US12183565

申请日：2008-07-31

Applicant: Ravi Pillarisetty ,  Been-Yih Jin ,  Willy Rachmady ,  Marko Radosavljevic

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Willy Rachmady ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L31/00

CPC classification number: H01L21/7624 ,  H01L21/02532 ,  H01L21/02664

Abstract: Germanium on insulator (GOI) semiconductor substrates are generally described. In one example, a GOI semiconductor substrate comprises a semiconductor substrate comprising an insulative surface region wherein a concentration of dopant in the insulative surface region is less than a concentration of dopant in the semiconductor substrate outside of the insulative surface region and a thin film of germanium coupled to the insulative surface region of the semiconductor substrate wherein the thin film of germanium and the insulative surface region are simultaneously formed by oxidation anneal of a thin film of silicon germanium (Si1-xGex) deposited to the semiconductor substrate wherein x is a value between 0 and 1 that provides a relative amount of silicon and germanium in the thin film of Si1-xGex.

Abstract translation: 绝缘体锗（GOI）半导体衬底通常被描述。 在一个示例中，GOI半导体衬底包括半导体衬底，其包括绝缘表面区域，其中绝缘表面区域中的掺杂剂的浓度小于绝缘表面区域外的半导体衬底中的掺杂剂的浓度和锗的薄膜 耦合到半导体衬底的绝缘表面区域，其中锗和绝缘表面区域的薄膜通过沉积到半导体衬底的硅锗薄膜（Si1-xGex）的氧化退火同时形成，其中x是 0和1，其在Si1-xGex的薄膜中提供相对量的硅和锗。

公开(公告)号：US07879675B2

公开(公告)日：2011-02-01

申请号：US12114227

申请日：2008-05-02

Applicant: Marko Radosavljevic ,  Suman Datta ,  Brian S. Doyle ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Amian Majumdar ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Suman Datta ,  Brian S. Doyle ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Amian Majumdar ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L29/41791 ,  H01L21/3141 ,  H01L23/485 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

Abstract translation: 一种半导体器件，包括形成在形成在半导体膜上的栅极电介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上的沟道区域附近。 源极和漏极区域各自包括与半导体沟道相邻并与其接触的半导体部分和与半导体部分相邻并与其接触的金属部分。

公开(公告)号：US20100155701A1

公开(公告)日：2010-06-24

申请号：US12317468

申请日：2008-12-23

Applicant: Marko Radosavljevic ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Ravi Pillarisetty

Inventor： Marko Radosavljevic ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Ravi Pillarisetty

IPC: H01L29/66

CPC classification number: H01L29/4236 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7783

Abstract: A self-aligned replacement metal gate QWFET device comprises a III-V quantum well layer formed on a substrate, a III-V barrier layer formed on the quantum well layer, a III-V etch stop layer formed on the III-V barrier layer, a III-V source extension region formed on the III-V etch stop layer and having a first sidewall, a source region formed on the III-V source extension region and having a second sidewall, a III-V drain extension region formed on the III-V etch stop layer and having a third sidewall, a drain region formed on the III-V drain extension region and having a fourth sidewall, a conformal high-k gate dielectric layer formed on the first, second, third, and fourth sidewalls and on a top surface of the etch stop layer, and a metal layer formed on the high-k gate dielectric layer.

Abstract translation: 自对准替代金属栅极QWFET器件包括形成在衬底上的III-V量子阱层，形成在量子阱层上的III-V势垒层，形成在III-V势垒层上的III-V蚀刻停止层 ，III-V源延伸区，形成在III-V蚀刻停止层上，并具有第一侧壁，形成在III-V源极延伸区上并具有第二侧壁的源极区， III-V蚀刻停止层并具有第三侧壁，形成在III-V漏极延伸区上并具有第四侧壁的漏极区，形成在第一，第二，第三和第四上的共形高k栅介质层 侧壁和蚀刻停止层的顶表面，以及形成在高k栅极电介质层上的金属层。

公开(公告)号：US20100148153A1

公开(公告)日：2010-06-17

申请号：US12316878

申请日：2008-12-16

Applicant: Mantu K. Hudait ,  Peter G. Tolchinsky ,  Robert S. Chau ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Aaron A. Budrevich

Inventor： Mantu K. Hudait ,  Peter G. Tolchinsky ,  Robert S. Chau ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Aaron A. Budrevich

IPC: H01L29/78

CPC classification number: H01L29/7784 ,  H01L29/365 ,  H01L29/66462

Abstract: A group III-V material device has a delta-doped region below a channel region. This may improve the performance of the device by reducing the distance between the gate and the channel region.

Abstract translation: III-V族材料器件在沟道区域下方具有δ掺杂区域。 这可以通过减小栅极和沟道区域之间的距离来改善器件的性能。

公开(公告)号：US20100078684A1

公开(公告)日：2010-04-01

申请号：US12632753

申请日：2009-12-07

Applicant: Willy Rachmady ,  Marko Radosavljevic ,  Mantu K. Hudait ,  Matthew V. Metz

Inventor： Willy Rachmady ,  Marko Radosavljevic ,  Mantu K. Hudait ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/20

CPC classification number: H01L21/0228 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/28273 ,  H01L21/312 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/517 ,  H01L29/78

Abstract: Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer.

Abstract translation: 本发明的实施例描述了一种制造具有低电流泄漏和高导通截止电流比的III-V量子阱晶体管的方法。 在半导体膜上形成具有开口的疏水性掩模。 该开口露出半导体膜上希望形成介电层的部分。 亲水表面形成在半导体膜的暴露部分上。 然后通过使用原子层沉积工艺在亲水表面上形成介电层。 金属层沉积在电介质层上。

公开(公告)号：US20100032763A1

公开(公告)日：2010-02-11

申请号：US12221802

申请日：2008-08-06

Applicant: Ravi Pillarisetty ,  Jack Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung

Inventor： Ravi Pillarisetty ,  Jack Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L21/26586 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/42312 ,  H01L29/66356 ,  H01L29/7391

Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.

Abstract translation: 微电子器件包括具有第一栅极和第二栅极的P-I-N（p +区域，本征半导体和n +区域）半导体。 第一栅极是设置在上表面平面上的栅极堆叠，并且第二栅极从超出第一平面的第二平面访问半导体本体。