公开(公告)号：US10741698B2

公开(公告)日：2020-08-11

申请号：US16355398

申请日：2019-03-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/088

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10411140B2

公开(公告)日：2019-09-10

申请号：US15892028

申请日：2018-02-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: B81B7/02 ,  H01L29/84 ,  H01H59/00 ,  B82B3/00 ,  H01H1/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US10388772B2

公开(公告)日：2019-08-20

申请号：US16013095

申请日：2018-06-20

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Salih Muhsin Celik

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/49

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

公开(公告)号：US10211257B2

公开(公告)日：2019-02-19

申请号：US15829397

申请日：2017-12-01

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars is stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

公开(公告)号：US10134899B2

公开(公告)日：2018-11-20

申请号：US14983070

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

公开(公告)号：US20180323301A1

公开(公告)日：2018-11-08

申请号：US16035458

申请日：2018-07-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/49 ,  H01L29/165 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/225

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

公开(公告)号：US10103252B2

公开(公告)日：2018-10-16

申请号：US15361935

申请日：2016-11-28

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/085 ,  H01L29/66 ,  H01L27/098 ,  H01L29/78 ,  H01L29/808 ,  H01L29/417 ,  H01L29/10 ,  H01L21/283 ,  H01L29/06

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

公开(公告)号：US10062690B2

公开(公告)日：2018-08-28

申请号：US15209662

申请日：2016-07-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/336 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/225 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US09865653B2

公开(公告)日：2018-01-09

申请号：US15293998

申请日：2016-10-14

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars ism stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

公开(公告)号：US09847260B2

公开(公告)日：2017-12-19

申请号：US14969393

申请日：2015-12-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.