公开(公告)号：US08477125B2

公开(公告)日：2013-07-02

申请号：US11641842

申请日：2006-12-20

Applicant: Hye Hyang Park ,  Byoung Deog Choi ,  Sun A Yang ,  Youn Chul Oh ,  Eun Jung Lee ,  Won Seok Kang

Inventor： Hye Hyang Park ,  Byoung Deog Choi ,  Sun A Yang ,  Youn Chul Oh ,  Eun Jung Lee ,  Won Seok Kang

IPC: G09G5/00

CPC classification number: H01L27/144 ,  H01L27/3269 ,  H01L31/145 ,  H01L31/153 ,  H01L31/1872 ,  Y02E10/50 ,  Y02P70/521

Abstract: An organic light-emitting display includes a substrate, a thin film transistor on the substrate, an organic light-emitting diode electrically connected to the thin film transistor, and a photo sensor having a plurality of photo diodes connected to one another in parallel.

Abstract translation: 有机发光显示器包括基板，基板上的薄膜晶体管，与薄膜晶体管电连接的有机发光二极管和具有并联连接的多个光电二极管的光电传感器。

公开(公告)号：US20130099100A1

公开(公告)日：2013-04-25

申请号：US13636720

申请日：2011-03-23

Applicant: Nikolai Pavlov

Inventor： Nikolai Pavlov

IPC: H01L27/144 ,  H01L31/09

CPC classification number: H01L27/144 ,  G01T1/248 ,  H01L31/09 ,  H01L31/107

Abstract: Silicon photomultiplier and readout method A silicon photomultiplier device is provided which comprises a first electrode arranged to provide a bias voltage to the device, a second electrode arranged as a ground electrode for the device, and a third electrode arranged to provide an output signal from the device using the second electrode as the output signal ground.

Abstract translation: 硅光电倍增管和读出方法提供了一种硅光电倍增器装置，其包括布置成向器件提供偏置电压的第一电极，被布置为器件的接地电极的第二电极和布置成提供来自所述器件的输出信号的第三电极 设备使用第二个电极作为输出信号地。

公开(公告)号：US08426921B2

公开(公告)日：2013-04-23

申请号：US13019130

申请日：2011-02-01

Applicant: Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yuri A. Vlasov

Inventor： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yuri A. Vlasov

IPC: H01L27/12

CPC classification number: H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

Abstract translation: 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

公开(公告)号：US08012592B2

公开(公告)日：2011-09-06

申请号：US11591333

申请日：2006-11-01

Applicant: Eugene A. Fitzgerald

Inventor： Eugene A. Fitzgerald

IPC: B32B9/04 ,  B32B13/04 ,  B32B9/00 ,  B32B19/00 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/14601 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/76254 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/144 ,  H01L27/1446 ,  H01L27/14683 ,  H01L27/15 ,  H01L27/156 ,  H01L31/0328 ,  H01L31/143 ,  H01L31/162 ,  H01L2924/0002 ,  Y10S438/933 ,  H01L2924/00

Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a semiconductor structure includes a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The semiconductor structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region, a monocrystalline silicon layer disposed over the insulating layer in the first region, and a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region. The second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon.

Abstract translation: 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。 在一种结构中，半导体结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。 半导体结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层，设置在第一区域中的绝缘层上的单晶硅层和设置在第一单晶的至少一部分上的第二单晶半导体层 半导体层在第二区域中并且不存在于第一区域中。 第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。

公开(公告)号：US20110199602A1

公开(公告)日：2011-08-18

申请号：US13029650

申请日：2011-02-17

Applicant: Suk Pil KIM ,  Yoon Dong Park ,  Dong Seok Suh ,  Young Gu Jin ,  Seung Hoon Lee

Inventor： Suk Pil KIM ,  Yoon Dong Park ,  Dong Seok Suh ,  Young Gu Jin ,  Seung Hoon Lee

IPC: G01C3/08 ,  H01L31/10 ,  H01L31/00

CPC classification number: H01L27/14607 ,  G01B11/22 ,  G01C3/08 ,  G01S7/4863 ,  G01S17/48 ,  H01L27/144 ,  H01L27/14641 ,  H01L31/02327 ,  H01L31/112

Abstract: A sensor, including a plurality of photo gate pairs on a semiconductor substrate, each of the photo gate pairs including a first photo gate and a second photo gate, a first shared floating diffusion region in the semiconductor substrate, and a plurality of first transmission transistors on the semiconductor substrate, wherein each of the plurality of first transmission transistors is adapted to transmit charges to the first shared floating diffusion region in response to a first transmission control signal, the charges being generated in the semiconductor substrate under the first photo gate of each of the plurality of photo gate pairs.

Abstract translation: 一种传感器，包括半导体衬底上的多个光栅对，每个光栅对包括第一光栅和第二光栅，半导体衬底中的第一共享浮动扩散区和多个第一透射晶体管 在半导体基板上，其中多个第一透射晶体管中的每一个适于响应于第一透射控制信号将电荷传输到第一共享浮动扩散区域，电荷在每个第一传输控制信号的第一光栅下的半导体衬底中产生 的多个光栅对。

公开(公告)号：US07948047B2

公开(公告)日：2011-05-24

申请号：US12417636

申请日：2009-04-03

Applicant: Po-Sheng Shih

Inventor： Po-Sheng Shih

IPC: H01L31/0376 ,  H01L31/036 ,  H01L31/0232

CPC classification number: H01L29/78633 ,  H01L27/12 ,  H01L27/144 ,  H01L29/78609 ,  H01L31/147

Abstract: An input display is provided in the present invention. The input display includes a thin film transistor (TFT) and a light blocking layer. The TFT includes a low-field electrode, a high-field electrode connected to the low-field electrode with a connecting section, and a field-effect area positioned on the connecting section and connected to the high-field electrode, wherein a PN junction field is formed in the field-effect area when the TFT is switched off. The light blocking layer corresponds to the high-field electrode and hides the field-effect area from all incident light from the TFT.

Abstract translation: 在本发明中提供输入显示。 输入显示器包括薄膜晶体管（TFT）和遮光层。 TFT包括低场电极，连接到具有连接部分的低场电极的高场电极和位于连接部分上并连接到高场电极的场效应区域，其中PN结 当TFT关闭时，在场效应区域中形成场。 遮光层对应于高场电极，并隐藏来自TFT的所有入射光的场效应区域。

公开(公告)号：US07897428B2

公开(公告)日：2011-03-01

申请号：US12131988

申请日：2008-06-03

Applicant: Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

Inventor： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

IPC: H01L27/12

CPC classification number: H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

Abstract translation: 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二键合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

公开(公告)号：US20100025787A1

公开(公告)日：2010-02-04

申请号：US11541975

申请日：2006-10-02

Applicant: Michael W. Geis ,  Steven J. Spector ,  Donna M. Lennon ,  Matthew E. Grein ,  Robert T. Schulein ,  Jung U. Yoon ,  Franz Xaver Kaertner ,  Fuwan Gan ,  Theodore M. Lyszczarz

Inventor： Michael W. Geis ,  Steven J. Spector ,  Donna M. Lennon ,  Matthew E. Grein ,  Robert T. Schulein ,  Jung U. Yoon ,  Franz Xaver Kaertner ,  Fuwan Gan ,  Theodore M. Lyszczarz

IPC: H01L31/0352 ,  H01L21/30 ,  H01L31/0232

CPC classification number: H01L27/144 ,  H01L31/102

Abstract: A Silicon photodetector contains an insulating substrate having a top surface and a bottom surface. A Silicon layer is located on the top surface of the insulating substrate, where the Silicon layer contains a center region, the center region being larger in thickness than the rest of the Silicon layer. A top Silicon dioxide layer is located on a top surface of the center region. A left wing of the center region and a right wing of the center region are doped. The Silicon photodetector also has an active region located within the center region, where the active region contains a tailored crystal defect-impurity combination and Oxygen atoms.

Abstract translation: 硅光电检测器包含具有顶表面和底表面的绝缘基底。 硅层位于绝缘基板的顶表面上，其中硅层包含中心区域，中心区域的厚度大于硅层的其余部分。 顶部二氧化硅层位于中心区域的顶表面上。 中心区域的左翼和中心区域的右翼被掺杂。 硅光电探测器还具有位于中心区域内的有源区域，其中有源区域包含定制的晶体缺陷 - 杂质组合和氧原子。

公开(公告)号：US20090294814A1

公开(公告)日：2009-12-03

申请号：US12131988

申请日：2008-06-03

Applicant: Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

Inventor： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

IPC: H01L31/00 ,  H01L21/00

CPC classification number: H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

Abstract translation: 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

公开(公告)号：US07544532B2

公开(公告)日：2009-06-09

申请号：US11582937

申请日：2006-10-17

Applicant: Robert P. Ginn ,  Kenneth A. Gerber ,  Andreas Hampp ,  Alexander C. Childs

Inventor： Robert P. Ginn ,  Kenneth A. Gerber ,  Andreas Hampp ,  Alexander C. Childs

IPC: H01L21/00 ,  H01L31/00

CPC classification number: H01L27/14683 ,  H01L27/144 ,  H01L27/1469 ,  H01L31/0304 ,  H01L31/184

Abstract: InSb infrared photodiodes and sensor arrays with improved passivation layers and methods for making same are disclosed. In the method, a passivation layer of AlInSb is deposited on an n-type InSb substrate using molecular beam epitaxy before photodiode detector regions are formed in the n-type substrate. Then, a suitable P+ dopant is implanted directly through the AlInSb passivation layer to form photodiode detector regions. Next, the AlInSb passivation layer is selectively removed, exposing first regions of the InSb substrate, and gate contacts are formed in the first regions of the InSb substrate. Then, additional portions of the AlInSb passivation layer are selectively removed above the photodiode detectors exposing second regions. Next, metal contacts are formed in the second regions, and bump contacts are formed atop the metal contacts. Then, an antireflection coating is applied to a side of the substrate opposite from the side having the metal and bump contacts. Forming the AlInSb passivation layer before the photodiode detector regions reduces the number of defects created in the n-type InSb substrate during fabrication in comparison to conventional methods and improves the noise performance of InSb photodiodes and sensor arrays incorporating the improved passivation layer.

Abstract translation: 公开了具有改进的钝化层的InSb红外光电二极管和传感器阵列及其制造方法。 在该方法中，在n型衬底中形成光电二极管检测器区域之前，使用分子束外延，在n型InSb衬底上沉积钝化层AlInSb。 然后，通过AlInSb钝化层直接注入合适的P +掺杂剂，以形成光电二极管检测器区域。 接下来，选择性地去除AlInSb钝化层，暴露InSb衬底的第一区域，并且在InSb衬底的第一区域中形成栅极接触。 然后，在暴露第二区域的光电二极管检测器上方选择性地去除AlInSb钝化层的附加部分。 接下来，在第二区域中形成金属触点，并且在金属触点顶部形成凸点触点。 然后，将抗反射涂层施加到与具有金属和凸块接触的一侧相对的基板的一侧。 与传统方法相比，在光电二极管检测器区域之前形成AlInSb钝化层减少了在制造期间在n型InSb衬底中产生的缺陷的数量，并且改善了纳入改进的钝化层的InSb光电二极管和传感器阵列的噪声性能。