公开(公告)号：US07709909B2

公开(公告)日：2010-05-04

申请号：US12040166

申请日：2008-02-29

Applicant: Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

IPC: H01L29/78

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成氧化物层，并在氧化物层上形成高k电介质层。 然后将氧化物层和高k电介质层在足够的温度下退火足够的时间以产生具有渐变介电常数的栅极电介质。

公开(公告)号：US07671471B2

公开(公告)日：2010-03-02

申请号：US12031409

申请日：2008-02-14

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Uday Shah ,  Chris E. Barns ,  Matthew V. Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Uday Shah ,  Chris E. Barns ,  Matthew V. Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert S. Chau

IPC: H01L21/48

CPC classification number: H01L21/82345 ,  H01L21/28229 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成第一介电层，然后在第一介电层内形成沟槽。 在衬底上形成第二电介质层之后，在第二介电层的第一部分上的沟槽内形成第一金属层。 然后在第一金属层上和第二介电层的第二部分上形成第二金属层。

公开(公告)号：US07514346B2

公开(公告)日：2009-04-07

申请号：US11297084

申请日：2005-12-07

Applicant: Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

Inventor： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

IPC: H01L21/4763

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Abstract translation: 本发明是一种半导体器件，其包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 栅极电极形成在半导体本体的顶表面上的栅电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。

公开(公告)号：US20090085082A1

公开(公告)日：2009-04-02

申请号：US11863211

申请日：2007-09-27

Applicant: Gilbert Dewey ,  Matthew Metz ,  Jack Kavalieros ,  Robert Chau

Inventor： Gilbert Dewey ,  Matthew Metz ,  Jack Kavalieros ,  Robert Chau

IPC: H01L29/94 ,  H01L23/58 ,  H01L21/8242 ,  H01L21/31

CPC classification number: H01L21/02189 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40

Abstract: Controlled deposition of HfO2 and ZrO2 dielectrics is generally described. In one example, a microelectronic apparatus includes a substrate and a dielectric film coupled with the substrate, the dielectric film including ZrO2 and HfO2 wherein the ratio of Zr to Hf in the dielectric film is about 5 to 10 atoms of Zr for every 1 atom of Hf to reduce ToxE or reduce Jox of the dielectric film.

Abstract translation: 通常描述HfO 2和ZrO 2电介质的受控沉积。 在一个示例中，微电子装置包括衬底和与衬底耦合的电介质膜，电介质膜包括ZrO 2和HfO 2，其中介电膜中的Zr与Hf的比率为每1个原子的约5至10个原子的Zr Hf以减少ToxE或减少电介质膜的Jox。

公开(公告)号：US20090057788A1

公开(公告)日：2009-03-05

申请号：US12288944

申请日：2008-10-24

Applicant: Michael L. Hattendorf ,  Justin K. Brask ,  Justin S. Sandford ,  Jack Kavalieros ,  Matthew V. Metz

Inventor： Michael L. Hattendorf ,  Justin K. Brask ,  Justin S. Sandford ,  Jack Kavalieros ,  Matthew V. Metz

IPC: H01L29/78

CPC classification number: H01L21/28114 ,  H01L21/26586 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

公开(公告)号：US20090039446A1

公开(公告)日：2009-02-12

申请号：US12287308

申请日：2008-10-07

Applicant: Matthew V. Metz ,  Suman Datta ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Robert S. Chau

Inventor： Matthew V. Metz ,  Suman Datta ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Robert S. Chau

IPC: H01L29/78

CPC classification number: H01L21/31691 ,  H01L21/02197 ,  H01L21/02269 ,  H01L21/02293 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/517

Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.

Abstract translation: 描述半导体器件。 该半导体器件包括形成在对高k栅极电介质层施加应变的基板上的高k栅极电介质层和形成在高k栅极电介质层上的金属栅电极。

公开(公告)号：US20090020792A1

公开(公告)日：2009-01-22

申请号：US11779284

申请日：2007-07-18

Applicant: Rafael Rios ,  Jack Kavalieros ,  Stephen M. Cea

Inventor： Rafael Rios ,  Jack Kavalieros ,  Stephen M. Cea

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

Abstract translation: 形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。 翅片的氧化部分隔离被氮化物盖保护的半导体主体。 然后可以去除氮化物盖。 热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

公开(公告)号：US20080315310A1

公开(公告)日：2008-12-25

申请号：US11765023

申请日：2007-06-19

Applicant: Willy Rachmady ,  Jack Kavalieros ,  Uday Shah

Inventor： Willy Rachmady ,  Jack Kavalieros ,  Uday Shah

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L21/84 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention relate to the fabrication of three-dimensional multi-gate transistor devices with high aspect ratio semiconductor bodies through the use of a high K dielectric material layer which is selectively wet etched to from a high K gate dielectric. In one specific embodiment, the high K gate dielectric comprises hafnium oxide, the etch stop layer comprises silicon oxide, and the etchant comprise phosphoric acid conditioned with silicon nitride.

Abstract translation: 本发明的实施例涉及通过使用从高K栅介质选择性湿蚀刻的高K电介质材料层来制造具有高纵横比半导体本体的三维多栅极晶体管器件。 在一个具体实施例中，高K栅极电介质包括氧化铪，蚀刻停止层包括氧化硅，蚀刻剂包括用氮化硅调节的磷酸。

公开(公告)号：US07439571B2

公开(公告)日：2008-10-21

申请号：US11120353

申请日：2005-05-02

Applicant: Mark L. Doczy ,  Mark Y. Liu ,  Jack Kavalieros ,  Justin K. Brask ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Mark Y. Liu ,  Jack Kavalieros ,  Justin K. Brask ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/788 ,  H01L29/76

CPC classification number: H01L29/495 ,  H01L21/268 ,  H01L21/823828 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/6659

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.

Abstract translation: 描述形成微电子结构的方法。 这些方法包括提供包括源极/漏极和栅极区域的衬底，其中栅极区域包括设置在栅极介电层上的金属层，然后激光退火衬底。

公开(公告)号：US07439113B2

公开(公告)日：2008-10-21

申请号：US10889535

申请日：2004-07-12

Applicant: Mark Doczy ,  Mitchell Taylor ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau ,  Jack Hwang

Inventor： Mark Doczy ,  Mitchell Taylor ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau ,  Jack Hwang

IPC: H01L29/78

CPC classification number: H01L21/823842

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

Abstract translation: 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 金属层可以具有最适于形成一种类型的晶体管的功函数，但是用于形成n型和p型晶体管。 可以例如通过离子注入来转换金属层的功函数，使其更适用于形成相反类型的晶体管。