公开(公告)号：US20240125992A1

公开(公告)日：2024-04-18

申请号：US18191550

申请日：2023-03-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Quentin ABADIE ,  Sandrine VILLENAVE

IPC: G02B5/28 ,  G01J3/28

CPC classification number: G02B5/288 ,  G01J3/2823 ,  G01J2003/2826

Abstract: The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, a resonant cavity comprising a first transparent layer, interposed between second and third mirror layers, and a diffraction grating formed in the first layer, wherein at least one of the cavities has a different thickness than another cavity.

公开(公告)号：US20240063235A1

公开(公告)日：2024-02-22

申请号：US18386859

申请日：2023-11-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Francois GUYADER ,  Sara PELLEGRINI ,  Bruce RAE

IPC: H01L27/146 ,  G01J1/44 ,  H01L31/107 ,  H04N25/70

CPC classification number: H01L27/1461 ,  G01J1/44 ,  H01L27/14634 ,  H01L31/107 ,  H04N25/70 ,  G01J2001/4466

Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

公开(公告)号：US11894382B2

公开(公告)日：2024-02-06

申请号：US17544665

申请日：2021-12-07

Applicant: STMicroelectronics France ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier Weber ,  Christophe Lecocq

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

公开(公告)号：US20240014341A1

公开(公告)日：2024-01-11

申请号：US18220069

申请日：2023-07-10

Applicant: STMicroelectronics (Research & Development) Limited ,  STMicroelectronics (Crolles 2) SAS

Inventor： Isobel NICHOLSON ,  Sara PELLEGRINI ,  Dominique GOLANSKI ,  Alexandre LOPEZ

IPC: H01L31/107 ,  H01L27/146 ,  H01L31/02 ,  H01L31/0352

CPC classification number: H01L31/107 ,  H01L27/14643 ,  H01L31/02027 ,  H01L27/1463 ,  H01L31/035281

Abstract: A device includes a single photon avalanche diode in a portion of a substrate, wherein the portion has an octagonal profile. The octagonal profile is delimited by a wall forming an octagonal contour around the portion. The device further includes an array of diodes, wherein each diode is located in a corner between four adjacent single photon avalanche diodes. Each single photon avalanche diode further includes a doped anode region. A shallow trench isolation is formed in each doped anode region. A polysilicon line forming a resistor is supported at the upper surface of the shallow trench isolation.

公开(公告)号：US20230420472A1

公开(公告)日：2023-12-28

申请号：US18465063

申请日：2023-09-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Axel CROCHERIE

IPC: H01L27/146

CPC classification number: H01L27/14627 ,  H01L27/14607 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/1462

Abstract: An image sensor is includes a plurality of pixels. Each of the pixels includes a silicon photoconversion region and a material that at least partially surrounds the photoconversion region. The material has a refraction index smaller than the refraction index of silicon, and the interface between the photoconversion region of the pixel and the material is configured so that at least one ray reaching the photoconversion region of the pixel undergoes a total reflection or a plurality of successive total reflections at the interface.

公开(公告)号：US20230408738A1

公开(公告)日：2023-12-21

申请号：US18361634

申请日：2023-07-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Vincent FARYS ,  Alain INARD ,  Olivier NOBLANC

IPC: G02B5/02 ,  C23C16/34 ,  C23C18/12 ,  C23C16/56

CPC classification number: G02B5/0263 ,  C23C16/345 ,  G02B5/0268 ,  C23C18/1208 ,  G02B5/0236 ,  C23C16/56

Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.

公开(公告)号：US20230387208A1

公开(公告)日：2023-11-30

申请号：US18197945

申请日：2023-05-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal CHEVALIER ,  Sebastien FREGONESE ,  Thomas ZIMMER

IPC: H01L29/10 ,  H01L29/732 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/1008 ,  H01L29/7322 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/0808 ,  H01L29/6625 ,  H01L29/6631

Abstract: A lateral bipolar transistor includes an emitter region doped with a first conductivity type, having a first width and a first average doping concentration; a collector region doped with the first conductivity type, having a second width greater than the first width of the emitter region and a second average doping concentration lower than the first average doping concentration ; and a base region positioned between the emitter and collector regions. The emitter, collector and base regions are arranged in a silicon layer on an insulator layer on a substrate. A substrate region that is deprived of the silicon and insulator layers is positioned on a side of the collector region. A bias circuit is coupled, and configured to deliver, to the substrate region a bias voltage. This bias voltage is controlled to modulate an electrostatic doping of the collector region.

公开(公告)号：US11817484B2

公开(公告)日：2023-11-14

申请号：US17935754

申请日：2022-09-27

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Leo Gave

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L29/518 ,  H01L29/6634

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

公开(公告)号：US20230290786A1

公开(公告)日：2023-09-14

申请号：US18118391

申请日：2023-03-07

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Sebastien CREMER ,  Frederic MONSIEUR ,  Alain FLEURY ,  Sebastien HAENDLER

IPC: H01L27/12 ,  H01L21/762 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/1203 ,  H01L21/76264 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53257

Abstract: A device includes an active semiconductor layer on top of and in contact with an insulating layer which overlies a semiconductor substrate. A transistor for the device includes a source region, a drain region, and a body region arranged in the active semiconductor layer. The body region of the transistor is electrically coupled to the semiconductor substrate using a conductive via that crosses through the insulating layer.

公开(公告)号：US20230290570A1

公开(公告)日：2023-09-14

申请号：US18176190

申请日：2023-02-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Marios BARLAS ,  Yannick LE FRIEC ,  Xavier FEDERSPIEL

IPC: H01G4/008 ,  H01G4/33 ,  H01G4/30 ,  H01G4/012 ,  H01G4/228

CPC classification number: H01G4/008 ,  H01G4/012 ,  H01G4/228 ,  H01G4/306 ,  H01G4/33

Abstract: A device includes a first layer, having a copper track located therein. The first layer is covered with a second layer including a cavity. The cavity exposes at least a portion of the track. The portion is covered with a third layer of titanium nitride doped with silicon.