公开(公告)号：US11750194B2

公开(公告)日：2023-09-05

申请号：US17150859

申请日：2021-01-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi Fujita ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidetomo Kobayashi

IPC: H03K19/173 ,  H03K19/17728 ,  H03K19/17772 ,  H03K19/17758

CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17758 ,  H03K19/17772

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US11721370B2

公开(公告)日：2023-08-08

申请号：US17232708

申请日：2021-04-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G11C7/02 ,  G11C7/06 ,  G11C14/00

CPC classification number: G11C7/06 ,  G11C14/0009

Abstract: To provide a novel semiconductor device.
The semiconductor device includes cell arrays and peripheral circuits; the cell arrays include memory cells; the peripheral circuits includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit; the first driver circuit and the second driver circuit have a function of supplying a selection signal to the cell array; the first amplifier circuit and the second amplifier circuit have a function of amplifying a potential input from the cell array; the third amplifier circuit and the fourth amplifier circuit have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit; the first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit include a region overlapping with the cell array; and the memory cells include a metal oxide in a channel formation region.

公开(公告)号：US11689829B2

公开(公告)日：2023-06-27

申请号：US17739726

申请日：2022-05-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Kiyoshi Kato

IPC: H04N25/75 ,  H01L27/146 ,  H01L27/12 ,  H03K5/24 ,  H04N25/772

CPC classification number: H04N25/75 ,  H01L27/1225 ,  H01L27/146 ,  H03K5/249 ,  H04N25/772

Abstract: Provided is a comparison circuit to which a negative voltage to be compared can be input directly. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The comparison circuit compares a negative voltage and a negative reference voltage and outputs a first output voltage from the first output terminal in response to the comparison result. The negative voltage is input to the first input terminal. A positive reference voltage is input to the second input terminal. The positive reference voltage is determined so that comparison is performed. The differential pair includes a first n-channel transistor and a second n-channel transistor each having a gate and a backgate. The first input terminal is electrically connected to the backgate of the first n-channel transistor. The second input terminal is electrically connected to the gate of the second n-channel transistor.

公开(公告)号：US11424246B2

公开(公告)日：2022-08-23

申请号：US17061920

申请日：2020-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Shionoiri ,  Hiroyuki Miyake ,  Kiyoshi Kato

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/13 ,  H01L27/115 ,  H01L29/786 ,  G11C16/04

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

公开(公告)号：US11355176B2

公开(公告)日：2022-06-07

申请号：US17048330

申请日：2019-04-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Hajime Kimura ,  Atsushi Miyaguchi ,  Tatsunori Inoue

IPC: G11C11/405 ,  G06F12/0893 ,  H01L27/108 ,  H01L27/12

Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.

公开(公告)号：US11158371B2

公开(公告)日：2021-10-26

申请号：US16956630

申请日：2018-12-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G11C11/24 ,  G11C14/00 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/56 ,  H01L27/12

Abstract: A novel memory device is provided.
The memory device including a plurality of memory cells arranged in a matrix, and each of the memory cells includes a transistor and a capacitor. The transistor includes a first gate and a second gate, which include a region where they overlap with each other with a semiconductor layer therebetween. The memory device has a function of operating in a “writing mode”, a “reading mode”, a “refresh mode”, and an “NV mode”. In the “refresh mode”, data retained in the memory cell is read, and then the read data is written to the memory cell again for first time. In the “NV mode”, data retained in the memory cell is read, the read data is written to the memory cell again for second time, and then a potential at which the transistor is turned off is supplied to the second gate. The “NV mode” operation enables data to be stored for a long time even when power supply to the memory cell is stopped. The memory cell can store multilevel data.

公开(公告)号：US11152366B2

公开(公告)日：2021-10-19

申请号：US16619190

申请日：2018-05-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takayuki Ikeda ,  Kiyoshi Kato ,  Yuta Endo ,  Junpei Sugao

IPC: H01L29/10 ,  H01L27/108 ,  G11C5/02 ,  G11C11/403 ,  G11C11/409 ,  H01L29/24

Abstract: A semiconductor device with a large storage capacity per unit area is provided. A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

公开(公告)号：US11114470B2

公开(公告)日：2021-09-07

申请号：US16616707

申请日：2018-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Tomoaki Atsumi

IPC: H01L27/12 ,  H01L27/108

Abstract: A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.

公开(公告)号：US11101300B2

公开(公告)日：2021-08-24

申请号：US16628920

申请日：2018-07-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki

IPC: H01L29/10 ,  H01L27/12

Abstract: A semiconductor device enabling high integration is provided. The semiconductor device includes a plug, two capacitors, and two transistors sharing one oxide semiconductor. Each of the transistors includes a stacked-layer structure of a gate insulator and a gate electrode over the oxide semiconductor and an insulator in contact with a side surface of the gate electrode. An opening between the two gate electrodes exposes the insulators in contact with the side surfaces of the gate electrodes, and the plug is in the opening. The capacitor is directly provided over the oxide semiconductor. The side surface area of the capacitor is larger than the projected area of the capacitor.

公开(公告)号：US11074962B2

公开(公告)日：2021-07-27

申请号：US16640206

申请日：2018-08-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G11C11/40 ,  G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  H01L27/108

Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.