公开(公告)号：US20250077346A1

公开(公告)日：2025-03-06

申请号：US18809302

申请日：2024-08-19

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10

Abstract: A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.

公开(公告)号：US20250061022A1

公开(公告)日：2025-02-20

申请号：US18939475

申请日：2024-11-06

Applicant: Silicon Motion, Inc

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu ,  Jian-Dong DU

IPC: G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

公开(公告)号：US20250045159A1

公开(公告)日：2025-02-06

申请号：US18926329

申请日：2024-10-25

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C11/56 ,  G11C16/26 ,  G11C29/02 ,  G11C29/04 ,  G11C29/52 ,  H03M13/11

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

公开(公告)号：US12189959B2

公开(公告)日：2025-01-07

申请号：US18129028

申请日：2023-03-30

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06 ,  H03M13/45 ,  G11C29/52 ,  H03M13/00 ,  H03M13/11

Abstract: The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

公开(公告)号：US20240403161A1

公开(公告)日：2024-12-05

申请号：US18621069

申请日：2024-03-28

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10

Abstract: The invention provides a method for accessing a flash memory module, wherein the method includes the steps of: classifying multiple read retry tables into at least a first group and a second group to establish a classifying and sorting table, wherein each of the multiple read retry tables records at least one reading voltage, and any two read retry tables do not have exactly the same reading voltage; selecting a first read retry table from the first group to read a page of a block of the flash memory module to generate first read data; and when a decoder fails to decode the first read data, selecting a second read retry table from the first group to read the page of the block of the flash memory module to generate second read data for the decoder to decode.

公开(公告)号：US20240211175A1

公开(公告)日：2024-06-27

申请号：US18391703

申请日：2023-12-21

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A data recovery method for a flash memory includes: during a first programming pass, programming a memory cell of the flash memory to a specific charge state, thereby to store middle page data and lower page data into the memory cell; reading the memory cell to back up one of the middle page data and the lower page data stored in the memory cell to another memory cell in the flash memory; upon detecting an error during or after a second programming pass, based on a current voltage of the memory cell and the backed-up one of the middle page data and the lower page data from the another memory cell of the flash memory, recovering the middle page data and the lower page data of the memory cell; and writing back the recovered middle page data and the recovered lower page data to the flash memory.

公开(公告)号：US20240152288A1

公开(公告)日：2024-05-09

申请号：US18412635

申请日：2024-01-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G11C11/5628 ,  G11C11/5642 ,  G06F2212/7201 ,  G06F2212/7206 ,  Y02D10/00

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US20240127894A1

公开(公告)日：2024-04-18

申请号：US18515691

申请日：2023-11-21

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/16

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

公开(公告)号：US11916569B2

公开(公告)日：2024-02-27

申请号：US17676853

申请日：2022-02-22

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: H03M13/00 ,  H03M13/09 ,  G06F11/10 ,  G11C11/56 ,  G11C16/10 ,  H03M13/15 ,  G11C16/26

CPC classification number: H03M13/098 ,  G06F11/108 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/10 ,  H03M13/1515 ,  H03M13/611 ,  G11C16/26 ,  G11C2211/5641

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

公开(公告)号：US20240028258A1

公开(公告)日：2024-01-25

申请号：US17869735

申请日：2022-07-20

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method for performing data management of a memory device with aid of targeted protection control and associated apparatus are provided. The method may include: receiving a first host command from a host device; sending a first operating command to a non-volatile (NV) memory to read first stored data from a first location within the NV memory; monitoring a read count of the first location to determine whether the read count of the first location reaches a read count threshold; monitoring at least one error bit count of other stored data of at least one other location within the NV memory to determine whether the at least one error bit count reaches an error bit count threshold; and starting a targeted protection procedure to process second stored data, for preventing the second stored data from being damaged by at least one reading behavior of the host device.