公开(公告)号：US20240371979A1

公开(公告)日：2024-11-07

申请号：US18774512

申请日：2024-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Pei-Hsiu Wu ,  Chih Ping Wang ,  Chih-Han Lin ,  Jr-Jung Lin ,  Yun Ting Chou ,  Chen-Yu Wu

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

公开(公告)号：US20240363425A1

公开(公告)日：2024-10-31

申请号：US18769679

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66795 ,  H01L27/088

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

公开(公告)号：US12125891B2

公开(公告)日：2024-10-22

申请号：US17244430

申请日：2021-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Liang Lu ,  Chang-Yin Chen ,  Chih-Han Lin ,  Chia-Yang Liao

IPC: H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

公开(公告)号：US12113122B2

公开(公告)日：2024-10-08

申请号：US18178140

申请日：2023-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Pei-Hsiu Wu ,  Chih Ping Wang ,  Chih-Han Lin ,  Jr-Jung Lin ,  Yun Ting Chou ,  Chen-Yu Wu

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7851

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

公开(公告)号：US12057343B2

公开(公告)日：2024-08-06

申请号：US17349741

申请日：2021-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/764 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.

公开(公告)号：US20240243011A1

公开(公告)日：2024-07-18

申请号：US18587477

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/76831 ,  H01L21/30608 ,  H01L21/30655 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/3065

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

公开(公告)号：US20240186186A1

公开(公告)日：2024-06-06

申请号：US18402245

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Te-Yung Liu ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L27/0886 ,  H01L27/0924

Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

公开(公告)号：US20240153827A1

公开(公告)日：2024-05-09

申请号：US18401866

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/28123 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

公开(公告)号：US11855217B2

公开(公告)日：2023-12-26

申请号：US17120814

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L23/535 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28008 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4991 ,  H01L29/66795 ,  H01L29/785

Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

公开(公告)号：US20230411483A1

公开(公告)日：2023-12-21

申请号：US18363968

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chen-Ping Chen ,  Hsiaowen Lee ,  Chih-Han Lin

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L21/02532

Abstract: In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.