公开(公告)号：US20030197217A1

公开(公告)日：2003-10-23

申请号：US10372044

申请日：2003-02-20

Applicant: STMicroelectronics S.r.I

Inventor： Luigi Pascucci

IPC: H01L021/336 ,  H01L029/788

CPC classification number: H01L29/7923 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28282

Abstract: An electrically-programmable memory cell programmed by means of injection of channel hot electrons into a charge-storage element capacitively coupled to a memory cell channel for modulating a conductivity thereof depending on a stored amount of charge. A first and a second spaced-apart electrode regions are formed in a semiconductor layer and define a channel region there between; at least one of the first and second electrode regions acts as a programming electrode of the memory cell. A control electrode is capacitively coupled to the charge-storage element. The charge-storage element is placed over the channel to substantially extend from the first to the second electrode regions, and is separated from the channel region by a dielectric layer. The dielectric layer has a reduced thickness in a portion thereof near the at least one programming electrode.

Abstract translation: 通过将通道热电子注入到电容耦合到存储单元通道的电荷存储元件来编程的电可编程存储单元，用于根据存储的电荷量来调制其电导率。 第一和第二间隔开的电极区域形成在半导体层中并在其间限定沟道区域; 第一和第二电极区域中的至少一个用作存储单元的编程电极。 控制电极电容耦合到电荷存储元件。 电荷存储元件放置在通道上，从第一至第二电极区域基本上延伸，并通过电介质层与沟道区分离。 电介质层在其至少一个编程电极附近的部分中具有减小的厚度。

公开(公告)号：US20030183869A1

公开(公告)日：2003-10-02

申请号：US10356351

申请日：2003-01-30

Applicant: STMicroelectronics S.r.I.

Inventor： Barbara Crivelli ,  Mauro Alessandri

IPC: H01L029/76

CPC classification number: H01L29/511 ,  H01L21/28273 ,  H01L21/3144

Abstract: A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

Abstract translation: 一种工艺制造用于具有多层电介质层的半导体器件的非易失性存储单元的互补电介质层。 该过程开始于使用常规技术形成隧道氧化物，因此形成非晶或多晶硅层。 在非晶或多晶硅层被表面清洁和钝化之后，多晶层的表面通过使用自由基氮直接氮化。 之后，通过CVD技术形成作为ONO层或单个硅层的互聚电介质。 可以在执行直接氮化步骤之前或之后立即执行用于限定浮动栅极的掩模。 通过组合氮氧化物层和随后的电介质获得的互聚电介质的等效电学厚度在ONO层或单硅层实施例中不超过130埃。

公开(公告)号：US20030147293A1

公开(公告)日：2003-08-07

申请号：US10328721

申请日：2002-12-23

Applicant: STMicroelectronics S.r.I.

Inventor： Antonino Geraci ,  Alberto Campisi ,  Lorenzo Bedarida ,  Simone Bartoli

IPC: G11C029/00

CPC classification number: G11C29/44

Abstract: An autotesting method of a cells matrix of a memory device is disclosed which comprises the steps of: reading the values contained in a plurality of the memory cells; comparing the read values with reference values; signalling mismatch of the read values with the reference values as an error situation; and storing the error situations. In the autotesting method, the reading, comparing, signalling, and storing steps are repeated for all the memory cells in an matrix column. The autotesting method according to the invention further comprises the steps of storing the positions of any columns having at least one one error situation; and repeating all of the preceding steps according to a step of scanning all the matrix columns.

Abstract translation: 公开了一种存储器件的单元矩阵的自动测试方法，其包括以下步骤：读取多个存储器单元中包含的值; 将读取的值与参考值进行比较; 读取值与参考值的信令不匹配作为错误情况; 并存储错误情况。 在自动测试方法中，对矩阵列中的所有存储单元重复读取，比较，信令和存储步骤。 根据本发明的自动测试方法还包括以下步骤：存储具有至少一个错误情况的任何列的位置; 并且根据扫描所有矩阵列的步骤重复所有前述步骤。

公开(公告)号：US20030123306A1

公开(公告)日：2003-07-03

申请号：US10325486

申请日：2002-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Polizzi ,  Maurizio Perroni

IPC: G11C007/00

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2281

Abstract: The memory device of the invention outputs the read data in a time starting from the rising edge of the external clock that is shorter than that of other known devices, because the output buffer has an array of master-slave pairs of flip-flops synchronized by respective timing signals derived from the internal clock signal. The array receives data from the state machine through the second internal bus and provides the data to be output to the output stage of the buffer enabled by the state machine. A logic circuit generates timing signals for the master-slave flip-flops, respectively as logic NAND and logic AND of the internal clock signal and of an enabling signal of the output stage of the buffer generated by the state machine. Moreover, the memory device includes a circuit, synchronized by the internal clock signal, that introduces a delay of the enabling signal of the output stage of the buffer equivalent to a period of the internal clock signal.

Abstract translation: 本发明的存储器件在从外部时钟的上升沿开始的时间内比其它已知器件的存储器件输出读出的数据，因为输出缓冲器具有通过触发器同步的主 - 从对的阵列 从内部时钟信号导出的各个定时信号。 该阵列通过第二个内部总线从状态机接收数据，并将数据输出到由状态机启用的缓冲区的输出级。 逻辑电路产生主从触发器的定时信号，分别作为状态机产生的内部时钟信号和缓冲器的输出级的使能信号的逻辑“与”和逻辑“与”。 此外，存储器件包括由内部时钟信号同步的电路，其引入与内部时钟信号的周期相当的缓冲器的输出级的使能信号的延迟。

公开(公告)号：US20030100154A1

公开(公告)日：2003-05-29

申请号：US10285363

申请日：2002-10-30

Applicant: STMicroelectronics S.r.I.

Inventor： Ferruccio Frisina ,  Antonio Pinto ,  Angelo Magri

IPC: H01L021/336

CPC classification number: H01L24/10 ,  H01L23/485 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L29/41741 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate region and source regions, and has a protective passivation layer arranged to cover the gate region. Advantageously, a wettable metal layer, deposited onto the passivation layer and the first-level metal layer, overlies said source regions. In this way, the additional wettable metal layer is made to act as a second-level metal.

Abstract translation: 利用MOS技术制造具有改进结构的电子功率器件，以在栅极区域的两侧具有栅极指状区域和相应的源极区域。 该器件具有布置成独立地接触栅极区域和源极区域的第一级金属层，并且具有覆盖栅极区域的保护性钝化层。 有利地，沉积在钝化层和第一级金属层上的可湿性金属层覆盖在所述源极区域上。 以这种方式，使附加的可湿性金属层作为二级金属。

公开(公告)号：US20030092237A1

公开(公告)日：2003-05-15

申请号：US10325289

申请日：2002-12-20

Applicant: STMicroelectronics S.r.I.

Inventor： Nicola Nastasi ,  Dorotea Arcidiacono ,  Stefano Mazzali

IPC: H01L021/336

CPC classification number: H01L27/11521

Abstract: A method is provided for manufacturing electronic non-volatile memory devices on a semiconductor substrate including a matrix of memory cells having floating gate regions formed on respective active areas and an oxide layer separating the active areas. The method may include forming sidewalls of the floating gate regions that are slanted with respect to a surface of the semiconductor substrate, forming a trench in the oxide layer following the formation of the floating gate regions, and forming a plug of polycrystalline silicon in the trench. The slanted sidewalls of the floating gate regions provide a lead-in for the formation of upper layers.

Abstract translation: 提供了一种用于在半导体衬底上制造电子非易失性存储器件的方法，该半导体衬底包括具有形成在各自的有源区上的浮动栅极区域和分离有源区域的氧化物层的存储器单元的矩阵。 该方法可以包括形成相对于半导体衬底的表面倾斜的浮动栅极区域的侧壁，在形成浮动栅极区域之后在氧化物层中形成沟槽，以及在沟槽中形成多晶硅插塞 。 浮动栅极区域的倾斜侧壁提供用于形成上层的引入。

公开(公告)号：US20030080955A1

公开(公告)日：2003-05-01

申请号：US10260717

申请日：2002-09-27

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Pulvirenti ,  Gregorio Bontempo

IPC: G09G005/00

CPC classification number: H02M3/073 ,  G09G3/36 ,  G09G3/3696 ,  G09G2330/02 ,  G09G2330/021 ,  H02M2001/0022 ,  Y10T307/747

Abstract: A regulated voltage-boosting device provides a charge-pump circuit, which has an input terminal receiving a first voltage and an output terminal supplying a second voltage higher than the first voltage. The regulated voltage-boosting device provides a plurality of voltage-boosting stages that can be selectively activated and deactivated. The regulated voltage-boosting device provides an automatic-selection circuit for activating a number of voltage-boosting stages which is correlated to the first voltage and to the second voltage.

Abstract translation: 稳压升压装置提供电荷泵电路，其具有接收第一电压的输入端和提供高于第一电压的第二电压的输出端。 调节升压装置提供可以选择性地激活和去激活的多个升压级。 调节升压装置提供一个自动选择电路，用于激活与第一电压和第二电压相关的多个升压级。

公开(公告)号：US20030067032A1

公开(公告)日：2003-04-10

申请号：US10267033

申请日：2002-10-07

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda

IPC: H01L021/8238 ,  H01L029/792 ,  H01L029/76 ,  H01L021/336 ,  H01L031/062 ,  H01L031/119 ,  H01L031/113 ,  H01L029/94

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923

Abstract: A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an nullLnull shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

Abstract translation: 一种用于制造双电荷存储位置电可编程存储单元的方法，包括在半导体衬底上形成中心绝缘栅极的步骤; 形成物理上分离的电荷限制层，堆叠在中心栅极侧的介质电荷捕获材料 - 电介质层堆叠部分，每个电荷限制层堆叠部分中的电荷捕获材料层形成电荷存储元件; 在每个电荷限制层堆叠部分上形成侧面控制栅极; 在侧控制门侧面形成存储单元源极/漏极区; 并将侧面控制门电连接到中央门。 在中心栅极侧面的电荷限制层堆叠部分中的每一个形成为“L”形，基底电荷限制层堆叠部分位于衬底表面上，并且垂直电荷限制层堆叠部分抵靠 绝缘门的相应侧。

公开(公告)号：US20030049895A1

公开(公告)日：2003-03-13

申请号：US10199964

申请日：2002-07-18

Applicant: STMicroelectronics S.r.I.

Inventor： Gianfranco Cerofolini ,  Giuseppe Ferla

IPC: H01L021/336 ,  H01L051/40 ,  H01L021/8234 ,  H01L021/8244

CPC classification number: H01L21/28167 ,  H01L29/51

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

Abstract translation: 公开了一种通过电介质栅极氧化物制造具有可控和可调制传导路径的MOS晶体管的方法，其中晶体管结构包括在两个硅板之间形成的电介质氧化物层，并且其中硅板全部悬垂在氧化物层周围以限定 具有基本上矩形横截面形状的底切。 该方法包括以下步骤：将硅板的表面化学改变成在底切中提供的不同的官能团与其余表面中的不同的官能团; 并且将底切中提供的官能团选择性地与具有可逆还原中心和分子长度基本上等于底切宽度的有机分子反应，从而与有机分子的每个末端建立共价键。

公开(公告)号：US20030034766A1

公开(公告)日：2003-02-20

申请号：US10197237

申请日：2002-07-15

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Zafarana ,  Claudia Castelli

IPC: G05F001/618

CPC classification number: H02M3/1584 ,  H02M2001/0009

Abstract: A voltage/current controller device, particularly for interleaving switching regulators, comprises: a DC/DC converter having a plurality of modules, with each module including a drive transistor pair connected in series between first and second supply voltage references, a current sensor connected to one transistor in the pair, and a current read circuit connected to the sensor. Advantageously, the read circuit comprises a transconductance amplifier connected across the current sensor to sense a voltage signal related to a load current being applied to each module, the transconductance amplifier reading the voltage signal with the transistor in the conducting state.