公开(公告)号：US20200264901A1

公开(公告)日：2020-08-20

申请号：US16276178

申请日：2019-02-14

Applicant: Xilinx, Inc.

Inventor： Rafael C. Camarota ,  David P. Schultz

IPC: G06F9/445 ,  G06F13/40

Abstract: Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.

公开(公告)号：US10749729B1

公开(公告)日：2020-08-18

申请号：US16424328

申请日：2019-05-28

Applicant: Xilinx, Inc.

Inventor： Alan C. Wong ,  Hong Sik Ahn ,  Edward Lee ,  Christopher J. Borrelli

IPC: H04L27/12 ,  H04B1/20 ,  H04L27/38 ,  H03G3/30 ,  H04B1/16 ,  H04L25/03

Abstract: A circuit includes an AGC adaptation circuit configured to receive a first signal generated based on an AGC output signal from an AGC circuit. The AGC circuit applies an AGC gain to an AGC input signal to generate the AGC output signal. The AGC adaptation circuit determines an observed value of the first signal, and determines a AGC adaptation step size based on the observed value and a predetermined target value associated with the first signal. The AGC adaptation circuit provides a second signal to adjust the AGC gain of the AGC circuit using the AGC adaptation step size.

公开(公告)号：US10749532B1

公开(公告)日：2020-08-18

申请号：US16291286

申请日：2019-03-04

Applicant: Xilinx, Inc.

Inventor： Mayank Raj ,  Didem Z. Turker Melek ,  Parag Upadhyaya ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03L1/02 ,  H03L7/093 ,  H03L7/099 ,  H03L7/07 ,  H03L7/10

Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

公开(公告)号：US10742254B1

公开(公告)日：2020-08-11

申请号：US16056236

申请日：2018-08-06

Applicant: Xilinx, Inc.

Inventor： Adrian Lynam

IPC: H04B1/525 ,  H03M1/10 ,  H03M1/00 ,  H04B1/04

Abstract: A leakage compensation circuit includes a compensation digital to analog converter (DAC) and an adjustment circuit. The compensation DAC is configured to: receive a first digital signal associated with a transmitter of a transceiver; generate a compensation analog signal using the first digital signal; and provide the compensation analog signal to a receiver of the transceiver. The adjustment circuit is configured to generate the first digital signal by adjusting a second digital signal from the transmitter based on one or more adjustment parameters.

公开(公告)号：US10727873B1

公开(公告)日：2020-07-28

申请号：US16373434

申请日：2019-04-02

Applicant: Xilinx, Inc.

Inventor： Gordon I. Old

IPC: H03M13/37 ,  G06F11/10 ,  G11C29/52 ,  H03M13/13

Abstract: A decoder circuit includes an input configured to receive an encoded message, and a decoding loop circuit including first and second memories, an update circuit, and a sort circuit. The decoding loop circuit is configured to perform list decoding to the encoded message by successively decoding a plurality of bits of a first codeword of the encoded message in a plurality of decoding loops respectively; and provide, to an output, a decoded message. In each decoding loop, the update circuit is configured to receive, from the first memory, parent path values, and provide, to a second memory, child path values based on the parent path values. The sort circuit is configured to receive, from the second memory, the child path values; and provide, to the first memory, surviving child path values based on the child path values.

公开(公告)号：US10726182B1

公开(公告)日：2020-07-28

申请号：US16100041

申请日：2018-08-09

Applicant: Xilinx, Inc.

Inventor： Sandeep S. Deshpande ,  Feng Cai ,  Saikat Bandyopadhyay

IPC: G06F17/50 ,  G06F30/3312 ,  G06F9/448 ,  G06F30/327

Abstract: Disclosed approaches involve simulating a circuit design specified in a hardware description language (HDL). During simulation, a thread is started at an edge of a simulation clock signal for evaluation of states of a finite state machine (FSM) that represent a series of events specified in a statement in the HDL. The thread transitions from one state to a next state in the FSM in response to evaluation of the one state. In response to encountering a fork state in the FSM, the thread is forked into two threads during simulation. The fork state represents a composite operator in the statement, and the FSM has a branch from the fork state for each operand of the composite operator. In response to encountering a join state in the FSM by the two threads, the two threads are joined into one thread.

公开(公告)号：US10726175B1

公开(公告)日：2020-07-28

申请号：US16291952

申请日：2019-03-04

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Satyaprakash Pareek ,  Bing Tian ,  Ashish Sirasao

IPC: G06F30/30 ,  H01L27/02 ,  G06F30/327 ,  G06F30/398 ,  G06F30/00

Abstract: A memory optimization method includes identifying, within a circuit design, a memory having an arithmetic operator at an output side and/or an input side of the memory. The memory may include a read-only memory (ROM). In some examples, an input of the arithmetic operator includes a constant value. In some embodiments, the memory optimization method further includes absorbing a function of the arithmetic operator into the memory. By way of example, the absorbing the function includes modifying contents of the memory based on the function of the arithmetic operator to provide an updated memory and removing the arithmetic operator from the circuit design.

公开(公告)号：US10686731B2

公开(公告)日：2020-06-16

申请号：US16226453

申请日：2018-12-19

Applicant: XILINX, INC.

Inventor： Steven L. Pope ,  Derek Roberts ,  David J. Riddoch ,  Dmitri Kitariev

IPC: H04L12/931 ,  H04L12/883 ,  H04L12/935 ,  H04L29/06 ,  H04L12/933 ,  H04L12/721

Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.

公开(公告)号：US20200183937A1

公开(公告)日：2020-06-11

申请号：US16212134

申请日：2018-12-06

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Bing Tian

IPC: G06F16/2453 ,  G06F16/2455 ,  G06F9/30

Abstract: Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.

公开(公告)号：US10680583B1

公开(公告)日：2020-06-09

申请号：US16286489

申请日：2019-02-26

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  Diarmuid Collins ,  Edward Cullen

IPC: G05F1/56 ,  G06F1/00 ,  H02M3/156 ,  H03K3/012 ,  G06F1/04

Abstract: A control circuit used in an integrated circuit device is described. The control circuit comprises a startup timer configured to generate a startup timing signal; a startup circuit configured to generate a startup control signal; and a switching element coupled between the startup circuit and a load; wherein the switching element applies the startup control signal to the load during a startup period associated with the startup timing signal. A method of controlling an operation of an integrated circuit device is also described.