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    Method for making semiconductor device with isolation pillars between adjacent semiconductor fins
    232.
    发明授权
    Method for making semiconductor device with isolation pillars between adjacent semiconductor fins 有权
    在相邻半导体鳍片之间制造具有隔离柱的半导体器件的方法

    公开(公告)号：US09281382B2

    公开(公告)日：2016-03-08

    申请号：US14295618

    申请日：2014-06-04

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

    IPC: H01L21/00 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

    CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/785

    Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

    Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成多个横向间隔开的半导体鳍片，以及在横向间隔开的半导体鳍片之间形成第一电介质材料的区域。 该方法还可以包括：从多个半导体鳍片中选择性地移除至少一个中间半导体鳍片，以限定第一介电材料的相应区域之间的至少一个沟槽，以及形成与第一电介质不同的第二电介质材料的区域 所述至少一个沟槽用于在相邻的半导体鳍片之间提供至少一个隔离柱。

    Semiconductor device providing enhanced fin isolation and related methods
    233.
    发明授权
    Semiconductor device providing enhanced fin isolation and related methods 有权
    提供增强散热片隔离和相关方法的半导体器件

    公开(公告)号：US09269712B2

    公开(公告)日：2016-02-23

    申请号：US14068340

    申请日：2013-10-31

    Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

    Inventor： Qing Liu ,  Ruilong Xie ,  Hyun-Jin Cho

    IPC: H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/06

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

    Abstract translation: 制造半导体器件的方法可以包括在包括第一半导体材料的衬底上形成第一半导体层，在包括第二半导体材料的第一半导体层上形成第二半导体层，以及在第二半导体层上形成掩模区域和蚀刻 通过第一和第二半导体层在衬底上限定多个间隔开的柱。 该方法可以进一步包括在横向围绕柱和掩模区域形成氧化物层，以及去除掩模区域并在横向相邻的每个柱顶上相应的氧化物层部分上形成内部间隔物。 该方法还可以包括通过相应的内部间隔物之间​​的第二半导体层进行蚀刻，以从每个支柱形成第二半导体材料的一对半导体鳍片，以及去除内部间隔物并在每个半导体鳍片之下形成氧化物。

    Method of making a semiconductor device using trench isolation regions to maintain channel stress
    235.
    发明授权
    Method of making a semiconductor device using trench isolation regions to maintain channel stress 有权
    使用沟槽隔离区域制造半导体器件以维持沟道应力的方法

    公开(公告)号：US09099565B2

    公开(公告)日：2015-08-04

    申请号：US14048282

    申请日：2013-10-08

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing Liu ,  Nicolas Loubet

    IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12

    CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203

    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region.

    Abstract translation: 用于形成互补金属氧化物半导体（CMOS）半导体器件的方法包括在绝缘体上硅（SOI）晶片的半导体层中形成横向相邻的第一和第二有源区。 应力诱导层形成在第一有源区上方以赋予应力。 沟槽隔离区形成为包围应力诱导层的第一有源区和相邻部分。 去除应力诱导层，离开沟槽隔离区域以保持赋予第一有源区域的应力。

    Dual channel hybrid semiconductor-on-insulator semiconductor devices
    236.
    发明授权
    Dual channel hybrid semiconductor-on-insulator semiconductor devices 有权
    双通道混合半导体绝缘体半导体器件

    公开(公告)号：US09059041B2

    公开(公告)日：2015-06-16

    申请号：US13933642

    申请日：2013-07-02

    Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat A l'Energie atomique et aux Energies alternatives

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

    IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02

    CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

    Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

    Abstract translation: 通过顶部半导体层和绝缘体上半导体（SOI）衬底的掩埋绝缘体层形成沟槽。 执行选择性外延以形成填充沟槽并与处理衬底的半导体材料外延对准的体半导体部分。 在顶部半导体层和体半导体部分上沉积至少一个电介质层，并且被图案化以在顶部半导体层和体半导体部分的选定区域上形成开口。 半导体合金材料直接在顶部半导体层和体半导体部分的物理暴露表面上沉积在开口内。 半导体合金材料在随后的退火中与下面的半导体材料混合。 在SOI区域和体区域的每一个内，根据半导体材料是否与半导体合金材料混合形成两种类型的半导体材料部分。

    Layer formation with reduced channel loss
    237.
    发明授权
    Layer formation with reduced channel loss 有权
    层形成减少了通道损耗

    公开(公告)号：US09000491B2

    公开(公告)日：2015-04-07

    申请号：US14309409

    申请日：2014-06-19

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

    IPC: H01L29/745 ,  H01L27/148 ,  H01L21/311 ,  H01L29/10 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/1033 ,  H01L29/04 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78

    Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

    Abstract translation: 可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。 可以在栅极区域和半导体器件区域上形成第一绝缘层。 可以在第一绝缘层上形成第二绝缘层。 可以在第二绝缘层上形成第三绝缘层。 可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。 可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

    Method for the formation of a protective dual liner for a shallow trench isolation structure
    238.
    发明授权
    Method for the formation of a protective dual liner for a shallow trench isolation structure 有权
    用于形成浅沟槽隔离结构的保护性双层衬垫的方法

    公开(公告)号：US08962430B2

    公开(公告)日：2015-02-24

    申请号：US13907237

    申请日：2013-05-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： Qing Liu ,  Nicolas Loubet ,  Bruce Doris

    IPC: H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/66477 ,  H01L21/76232 ,  H01L21/76283 ,  H01L29/0649

    Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.

    Abstract translation: 在由第一半导体层，绝缘层和第二半导体层形成的衬底上，沉积氧化硅衬垫层和氮化硅衬垫层以形成掩模。 掩模用于打开通过第一半导体层和绝缘层并进入第二半导体层的沟槽。 二氧化硅和氮化硅的双衬垫共形沉积在沟槽内。 沟槽填充有二氧化硅。 氢氟酸蚀刻将氮化硅衬垫层与一部分共形氮化硅衬垫一起去除。 热磷酸蚀刻去除氧化硅衬垫层，填充沟槽的氧化硅的一部分和保形氮化硅衬垫的一部分。 双衬垫在第一和第二半导体层之间的沟槽的边缘处防止衬底蚀刻。

    TRANSISTOR HAVING A STRESSED BODY
    239.
    发明申请
    TRANSISTOR HAVING A STRESSED BODY 审中-公开
    具有受压身体的晶体管

    公开(公告)号：US20150008521A1

    公开(公告)日：2015-01-08

    申请号：US14494979

    申请日：2014-09-24

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

    IPC: H01L29/78 ,  H01L21/266 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06

    CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

    Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

    Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

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