公开(公告)号：US09136331B2

公开(公告)日：2015-09-15

申请号：US13860427

申请日：2013-04-10

Applicant: Micron Technology, Inc.

Inventor： Chris Larsen ,  Alex J. Schrinsky ,  John D. Hopkins ,  Matthew King

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L29/0657 ,  H01L21/743 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

Abstract translation: 一些实施例包括具有通过至少一个虚拟突起彼此间隔开的两个台面的半导体材料的半导体结构。 虚拟突起具有沿X的横截面的宽度，并且台面具有至少3X的横截面的宽度。 一些实施例包括具有存储器阵列区域和与存储器阵列区域相邻的外围区域的半导体结构。 周边区域内的半导体材料被图案化成两个相对较宽的台面，其彼此间隔开至少一个较窄的突起。 相对窄的突起具有沿X的横截面的宽度，并且相对宽的台面具有至少3X的横截面的宽度。

公开(公告)号：US20140217349A1

公开(公告)日：2014-08-07

申请号：US13759707

申请日：2013-02-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John D. Hopkins

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/249 ,  H01L45/1226 ,  H01L45/144

Abstract: Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.

Abstract translation: 一些实施例包括在交替导电字线电平和电绝缘水平的叠层内具有导电位线的构造。 腔体延伸到导电字线水平，相变材料在腔内。 一些实施例包括形成存储器的方法。 通过交替导电水平和电绝缘水平的堆叠形成开口。 腔体沿着开口延伸到导电水平。 相变材料形成在空腔内，并且并入垂直堆叠的存储单元中。 导电互连形成在开口内，并且与多个垂直堆叠的存储单元电耦合。

公开(公告)号：US20140191306A1

公开(公告)日：2014-07-10

申请号：US13735908

申请日：2013-01-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John D. Hopkins

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L29/7889 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7926

Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

Abstract translation: 一些实施例包括形成垂直存储器串的方法。 形成沟槽以延伸通过交替导电水平和电绝缘水平的堆叠。 在沟槽内形成电绝缘面板。 去除面板的一些部分以形成开口。 每个开口具有沿堆叠的第一对相对侧，并且具有沿面板的剩余部分的第二对相对侧。 腔形成为沿着开口的第一对相对侧延伸到导电水平。 在空腔内形成电荷阻挡材料和电荷储存材料。 通道材料形成在开口内并且通过栅极电介质材料与电荷存储材料间隔开。 一些实施例包括半导体结构，并且一些实施例包括形成垂直堆叠结构的方法。

公开(公告)号：US20250167130A1

公开(公告)日：2025-05-22

申请号：US19030527

申请日：2025-01-17

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Harsh Narendrakumar Jain ,  John D. Hopkins ,  Xiaosong Zhang

IPC: H01L23/544

Abstract: An electronic device comprising a multideck structure including a base stack of materials and one or more stacks of materials on the base stack of materials, at least one high aspect ratio feature in an array region in the base stack of materials and in the one or more stacks of materials, and overlay marks including an optical contrast material in or on only an upper portion of the base stack of materials in an overlay mark region of the electronic device is disclosed. The overlay mark region is laterally adjacent to the array region and the overlay marks are adjacent to at least one additional high aspect ratio feature in the base stack of materials. Additional electronic devices and memory devices are disclosed.

公开(公告)号：US12295140B2

公开(公告)日：2025-05-06

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US12288585B2

公开(公告)日：2025-04-29

申请号：US17396056

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Purnima Narayanan ,  Vinayak Shamanna ,  Justin D. Shepherdson

IPC: H10B41/10 ,  G11C16/04 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material. The upper conductive tiers comprise sacrifice material that is of different composition from that of the conducting material, the insulating material, and the insulative material. The sacrifice material is replaced with conductive material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US12279420B2

公开(公告)日：2025-04-15

申请号：US17723716

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

IPC: H10B41/27 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H10B43/27

Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

公开(公告)号：US20250104770A1

公开(公告)日：2025-03-27

申请号：US18974232

申请日：2024-12-09

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. The insulative tier immediately-above a lowest of the conductive tiers comprises a lower first insulating material and an upper second insulating material above the upper first insulating material. The upper second insulating material is of different composition from that of the lower first insulating material. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US12230325B2

公开(公告)日：2025-02-18

申请号：US17409300

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

IPC: H01L21/768 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US12219762B2

公开(公告)日：2025-02-04

申请号：US17571216

申请日：2022-01-07

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins

IPC: H10B43/27 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises sacrificial material of different composition from the first-tier material there-above and from the second-tier material tier there-above. The sacrificial material is of different composition from that of an uppermost portion of the conductor material of the conductor tier. The sacrificial material is isotropically etched selectively relative to the uppermost portion of the conductor material of the conductor tier, selectively relative to the first-tier material there-above, and selectively relative to the second-tier material there-above. After the isotropic etching, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other methods and structure independent of method are disclosed.