公开(公告)号：US09245648B1

公开(公告)日：2016-01-26

申请号：US14498519

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaonan Chen ,  Xiao Lu

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/5692 ,  G11C17/16

Abstract: In a one-time-programming (OTP) memory cell, dual-voltage sensing is utilized to determine whether the memory cell has experienced a non/soft breakdown or a hard breakdown. The drain current of the memory cell is read when the gate voltage is at a first predetermined voltage, and if the read drain current is greater than a predetermined current level, then a hard breakdown is detected. One or more additional readings of the current may be obtained to determine that a hard breakdown has occurred. If the read drain current is less than the predetermined current level, then a non/soft breakdown is detected. The threshold voltage of the memory cell may be shifted, and a second reading of the drain current may be obtained when the gate voltage is at a second predetermined voltage in case the memory cell experiences a non/soft breakdown.

Abstract translation: 在一次编程（OTP）存储器单元中，利用双电压感测来确定存储器单元是否经历了非/软故障或硬故障。 当栅极电压处于第一预定电压时，读取存储单元的漏极电流，并且如果读取的漏极电流大于预定电流电平，则检测到硬故障。 可以获得电流的一个或多个附加读数以确定发生了硬故障。 如果读漏极电流小于预定电流电平，则检测到非/软击穿。 当存储器单元经历非/软击穿时，当栅极电压处于第二预定电压时，可以移位存储单元的阈值电压，并且可以获得漏极电流的第二读数。

公开(公告)号：US09153642B2

公开(公告)日：2015-10-06

申请号：US13784895

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H01L49/02 ,  H01L23/522 ,  H01L27/07 ,  H01L29/94

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/88 ,  H01L28/92 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure.

Abstract translation: 特定的金属氧化物金属（MOM）电容器器件包括耦合到衬底的导电栅极材料。 MOM电容器装置还包括耦合到导电栅极材料的第一金属结构。 MOM电容器装置还包括耦合到衬底并且靠近第一金属结构的第二金属结构。

公开(公告)号：US09105310B2

公开(公告)日：2015-08-11

申请号：US13759310

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

IPC: G11C11/34 ,  G11C11/40 ,  G11C17/12 ,  G11C5/02 ,  G11C7/00 ,  G11C17/16 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  G11C7/12 ,  G11C11/404

CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

Abstract: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage.

Abstract translation: 一种方法包括在包括重叠区域和沟道区域的半导体晶体管结构下产生击穿条件。 通过使半导体晶体管结构的栅极和重叠区域之间的第一电压差超过半导体晶体管结构的击穿电压，同时保持栅极和沟道区域之间的第二电压差小于 击穿电压。

公开(公告)号：US20150187774A1

公开(公告)日：2015-07-02

申请号：US14659893

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L27/092 ,  H01L29/06 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin-type semiconductor device comprises means for providing a first fin-type conduction channel having first and second regions, means for providing a second fin-type conduction channel having a fourth region above a third region, and means for shielding current leakage coupled to at least one of the first region and the third region. The first region has a first doping concentration greater than a second doping concentration of the second region. The first fin-type conduction channel comprises first ion implants implanted into the substrate at a first depth and second ion implants implanted into the substrate at a different depth. The third region has a third doping concentration, and the fourth region has a fourth doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括用于提供具有第一和第二区域的第一鳍式传导沟道的装置，用于提供具有在第三区域上方的第四区域的第二鳍式传导沟道的装置，以及用于屏蔽漏电耦合到 第一区域和第三区域中的至少一个。 第一区域具有大于第二区域的第二掺杂浓度的第一掺杂浓度。 第一鳍型传导通道包括在第一深度处植入衬底中的第一离子植入物和在不同深度处植入衬底中的第二离子植入物。 第三区域具有第三掺杂浓度，第四区域具有第四掺杂浓度。

公开(公告)号：US09043740B2

公开(公告)日：2015-05-26

申请号：US14048918

申请日：2013-10-08

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: G06F17/50 ,  H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/32 ,  H01F41/30 ,  H01F41/32 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  G06F17/5068 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/309 ,  H01F41/32 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

Abstract translation: 公开了一种磁性隧道接合装置及其制造方法。 在特定实施例中，非暂时计算机可读介质包括处理器可执行指令。 当处理器执行时，指令使处理器开始在磁隧道结结构的自由层上沉积封盖材料以形成覆盖层。 所述指令在由所述处理器执行时使得所述处理器开始所述封盖材料的第一层的氧化以形成氧化材料的第一氧化层。

公开(公告)号：US09041131B2

公开(公告)日：2015-05-26

申请号：US14246165

申请日：2014-04-07

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang

IPC: H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

Abstract translation: 形成磁性隧道结（MTJ）装置的方法包括在MTJ结构上形成第一MTJ盖层。 第一MTJ盖层包括第一非硝化金属。 该方法还包括在第一MTJ盖层上形成第二MTJ盖层。 第二MTJ盖层包括第二非硝化金属。 该方法还包括在第二MTJ盖层上形成顶部电极层。 第二MTJ盖层是导电的并且被配置为减少或防止氧化。

公开(公告)号：US09029170B2

公开(公告)日：2015-05-12

申请号：US13734685

申请日：2013-01-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li

IPC: H01L21/00 ,  H01L21/67 ,  G11C11/16 ,  H01L43/08 ,  H01L43/12 ,  H01L29/66 ,  H01L29/82 ,  H01L27/22

CPC classification number: H01L21/67011 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/53165

Abstract: A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process includes applying reverse photo etching to remove material that is not directly over the trench. The process also includes plagiarizing the MTJ structure without performing a photo-etch process on the MTJ structure.

Abstract translation: 通过包括在衬底中形成沟槽并在沟槽内沉积MTJ结构的工艺形成磁隧道结（MTJ）器件。 MTJ结构包括底电极，固定层，隧道势垒层，自由层和顶电极。 该方法包括施加反向光刻蚀以除去不直接在沟槽上的材料。 该方法还包括抄袭MTJ结构，而不对MTJ结构执行光蚀刻工艺。

公开(公告)号：US08999792B2

公开(公告)日：2015-04-07

申请号：US13834594

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L21/336 ,  H01L29/786 ,  G06F17/50 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The fin type semiconductor device also comprises an oxide layer. Prior to source and drain formation of the fin-type semiconductor device, a doping concentration of the oxide layer is less than the first doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括鳍，其包括具有第一掺杂浓度的第一区域和具有第二掺杂浓度的第二区域。 第一掺杂浓度大于第二掺杂浓度。 翅片型半导体器件还包括氧化物层。 在鳍式半导体器件的源极和漏极形成之前，氧化物层的掺杂浓度小于第一掺杂浓度。

公开(公告)号：US20150050785A1

公开(公告)日：2015-02-19

申请号：US14496225

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L21/8238 ,  H01L21/84 ,  H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在具体示例中，形成CMOS器件的方法包括在晶片的延伸层上形成第一层，在第一层的一部分上形成第一栅极，以及形成靠近延伸层的扩张区域。 该方法还包括去除第一栅极的一部分以产生空腔并去除第一层的一部分以将空腔延伸到延伸层。

公开(公告)号：US20140264485A1

公开(公告)日：2014-09-18

申请号：US13834594

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L29/66 ,  G06F17/50 ,  H01L29/78

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The fin type semiconductor device also comprises an oxide layer. Prior to source and drain formation of the fin-type semiconductor device, a doping concentration of the oxide layer is less than the first doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括鳍，其包括具有第一掺杂浓度的第一区域和具有第二掺杂浓度的第二区域。 第一掺杂浓度大于第二掺杂浓度。 翅片型半导体器件还包括氧化物层。 在鳍式半导体器件的源极和漏极形成之前，氧化物层的掺杂浓度小于第一掺杂浓度。