公开(公告)号：US10241849B2

公开(公告)日：2019-03-26

申请号：US16022791

申请日：2018-06-29

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/10 ,  H03M13/00 ,  G06F11/07 ,  H03M13/09 ,  H03M13/29 ,  G06F3/06 ,  G06F13/42 ,  H04L1/00 ,  H04L1/08 ,  H04L1/18 ,  G06F11/14

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

公开(公告)号：US10192609B2

公开(公告)日：2019-01-29

申请号：US15633677

申请日：2017-06-26

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4093 ,  H04L7/00

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US10191866B2

公开(公告)日：2019-01-29

申请号：US15665284

申请日：2017-07-31

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  G06F12/1081 ,  G11C7/10 ,  H05K1/18 ,  G11C5/04

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

公开(公告)号：US10152408B2

公开(公告)日：2018-12-11

申请号：US14566411

申请日：2014-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F12/00 ,  G06F12/02

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

公开(公告)号：US10149383B2

公开(公告)日：2018-12-04

申请号：US15814180

申请日：2017-11-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: G11C5/06 ,  H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F13/16 ,  G06F13/40 ,  G06F1/18 ,  G11C5/04 ,  G11C7/10

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US10095565B2

公开(公告)日：2018-10-09

申请号：US14855271

申请日：2015-09-15

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  H03M13/03 ,  H04L1/00 ,  H04L1/08 ,  H04L1/18 ,  G06F11/00 ,  G11C29/52 ,  G06F3/06

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

公开(公告)号：US20180108387A1

公开(公告)日：2018-04-19

申请号：US15793029

申请日：2017-10-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1045 ,  G11C7/1087 ,  G11C2207/105

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

公开(公告)号：US20180107542A1

公开(公告)日：2018-04-19

申请号：US15794164

申请日：2017-10-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20180039416A1

公开(公告)日：2018-02-08

申请号：US15642860

申请日：2017-07-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C11/4091

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US09881663B2

公开(公告)日：2018-01-30

申请号：US15175933

申请日：2016-06-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C11/34 ,  G11C11/4093 ,  G11C5/04 ,  H01L25/065 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  H01L25/18 ,  H01L23/00

CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/08148 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80897 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.